EP1M350 datasheet(16/86 Pages) ALTERA

16 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Each LAB contains dedicated logic for driving control signals to its LEs.

The control signals include clock, clock enable, asynchronous clear,

asynchronous preset, asynchronous load, synchronous clear, and

synchronous load signals. A maximum of six control signals can be used

at a time. Although synchronous load and clear signals are generally used

when implementing counters, they can also be used with other functions.

Each LAB can use two clocks and two clock enable signals. Each LAB’s

clock and clock enable signals are linked (e.g., any LE in a particular LAB

using LABCLK1 will also use LABCLKENA1). In addition to LAB-wide

control of clock enables, Mercury devices can also control clock enable

signals on individual LEs, allowing more than two clock enables in a

given LAB. The Quartus II software automatically chooses whether a

clock enable is LAB-wide for individual LEs. If both the rising and falling

edges of a clock are used in a LAB, both LAB-wide clock signals are used.

The LAB local interconnect, fast global signals, row-global signals, and

dedicated clock pins can generate the LAB-wide control signals. The

multi-level FastTrack Interconnect’s inherent low skew allows it to be

used for clock distribution. Figure 6 shows the LAB control signal

generation circuit.

EP1M350 数据表(PDF) 16 Page - Altera Corporation