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数据搜索系统，热门电子元器件搜索 |
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EP1M350 数据表(PDF) 40 Page - Altera Corporation |
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EP1M350 数据表(HTML) 40 Page - Altera Corporation |
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40 / 86 page  40 Altera Corporation Mercury Programmable Logic Device Family Data Sheet Input/Output Clock Mode An ESB using input/output clock mode can also use up to four clocks. On each of the two ports, A or B, one clock controls all registers for inputs into the ESB: data input, WE, RE, read address, and write address. The other clock controls the ESB data output registers. Each ESB port, A or B, also supports independent read clock enable, write clock enable, and asynchronous clear signals. Input/output clock mode is commonly used for applications where the reads and writes occur at the same system frequency, but require different clock enable signals for the input and output registers. Figure 20 shows the ESB in input/output clock mode. |
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