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ATmega16HVB 数据表(PDF) 155 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 155 Page - ATMEL Corporation |
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155 / 273 page  155 8042A–AVR–07/09 ATmega16HVB/32HVB 26.2 Register Description 26.2.1 CBCR – Cell Balancing Control Register • Bit 7:4 – Res: Reserved Bits These bits are reserved bits in the ATmega16HVB/32HVB and will always read as zero. • Bit 3 – CBE4: Cell Balancing Enable 4 When this bit is set, the integrated Cell Balancing FET between terminals PV4 and PV3 will be enabled. When the bit is cleared, the Cell Balancing FET will be disabled. The Cell Balancing FETs are always disabled in Power-off mode. CBE4 cannot be set if CBE3 is set. • Bit 2 – CBE3: Cell Balancing Enable 3 When this bit is set, the integrated Cell Balancing FET between terminals PV3 and PV2 will be enabled. When the bit is cleared, the Cell Balancing FET will be disabled. The Cell Balancing FETs are always disabled in Power-off mode. CBE3 cannot be set if CBE2 or CBE4 is set. • Bit 1 – CBE2: Cell Balancing Enable 2 When this bit is set, the integrated Cell Balancing FET between terminals PV2 and PV1 will be enabled. When the bit is cleared, the Cell Balancing FET will be disabled. The Cell Balancing FETs are always disabled in Power-off mode. CBE2 cannot be set if CBE1 or CBE3 is set. • Bit 0 – CBE1: Cell Balancing Enable 1 When this bit is set (one), the integrated Cell Balancing FET between terminals PV1 and NV will be enabled. When the bit is cleared (zero), the Cell Balancing FET will be disabled. The Cell Bal- ancing FETs are always disabled in Power-off mode. CBE1 cannot be set if CBE2 is set. Bit 7 654 32 10 (0xF1) – – – – CBE4 CBE3 CBE2 CBE1 CBCR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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