ATmega16HVB datasheet(153/273 Pages) ATMEL

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153

8042A–AVR–07/09

ATmega16HVB/32HVB

25.4

25.4.1

FCSR – FET Control and Status Register

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega16HVB/32HVB, and will always read as zero.

• Bit 3 – DUVRD: Deep Under-voltage Recovery Disabled

When the DUVRD is cleared (zero), the FET Driver will be forced to operate in Deep Under-volt-

age Recovery DUVR mode. See ”DUVR - Deep Under Voltage Recovery Mode without Pre-

charge FET” on page 150 for details. To avoid that the FET driver tries to switch on the C-FET

during current protection or during internal reset, the DUVRD bit is overridden to one by hard-

ware in these cases. When this bit is set (one), Deep Under-voltage Recovery mode of the FET

Driver will be disabled.

• Bit 2 – CPS: Current Protection Status

The CPS bit shows the status of the Current Protection. This bit is set (one) when a Current Pro-

tection is active, and cleared (zero) otherwise.

• Bit 1 – DFE: Discharge FET Enable

When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of

the Battery Protection circuitry. When this bit is set (one), the Discharge FET is enabled. This bit

will automatically be cleared by the CBP circuitry when Current Protection is activated. When

this bit is cleared, Short-circuit, Discharge High-current and Discharge Over-current are disabled

regardless of the settings in the BPCR Register.

• Bit 0 – CFE: Charge FET Enable

When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of

the Battery Protection circuitry. When this bit is set (one), the Charge FET is enabled. This bit

will automatically be cleared by the CBP circuitry when Current Protection is activated. When

this bit is cleared and the DUVRD bit is set, Charge High-current Protection and Charge Over-

current Protection are disabled regardless of the settings in the BPCR Register. When the

DUVRD bit is cleared, the charge FET will be enabled by DUVR mode regardless of the CFE

status.

Notes:

1. Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator

cycles + 3 CPU clock cycles is required between each time the FCSR register is written. Any

writing to the FCSR register during this period will be ignored.

2. The NFET drivers require a minimum total cell voltage of 6V or higher or a charger connected

to turn-on the FETs. Note that this limit only applies if the FET is disabled in advanced. If the

FET is already enabled, the FET will be fully operational in the entire voltage range of the

device (4-25V).

Bit

(0xF0)

–

DUVRD

CPS

DFE

CFE

FCSR

Read/Write

R/W

Initial Value

ATmega16HVB 数据表(PDF) 153 Page - ATMEL Corporation

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