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ADP2116ACPZ-R7 数据表(PDF) 30 Page - Analog Devices

部件名 ADP2116ACPZ-R7
功能描述  Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2116ACPZ-R7 数据表(HTML) 30 Page - Analog Devices

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ADP2116
Rev. 0 | Page 30 of 36
5.
Calculate the compensation component values of the
feedback loop by using the following equation:
⎟⎟
⎜⎜
×
⎟⎟
⎜⎜
×
=
REF
OUT
OUT
CS
m
CROSS
COMP
V
V
C
G
g
f
R
)
π
2
(
9
.
0
where:
gm = 550 μS.
GCS = 4 A/V.
VREF = 0.6 V.
VOUT = 2.5 V.
COUT = 0.8 × 69 μF (capacitance derated by 20% to account
for dc bias).
Therefore, from Equation 18,
RCOMP = 30 kΩ.
Substituting RCOMP in Equation 19 yields CCOMP = 820 pF.
Table 10. Channel 1 Circuit Settings
Circuit Parameter
Setting
Value
Output Voltage, VOUT
See Step 1
2.5 V
Reference Voltage, VREF
Fixed, typical
0.6 V
Error Amplifier Transconductance, gm
Fixed, typical
550 μS
Current-Sense Gain, GCS
Fixed, typical
4 A/V
Switching Frequency, fSW
See Step 2
600 kHz
Crossover Frequency, fCROSS
1/12 fSW
50 kHz
Zero Frequency, fZERO
1/8 fCROSS
6.25 kHz
Output Inductor, LOUT
See Step 3
3.3 μH
Output Capacitor, COUT
See Step 4
(47 + 22) μF
Compensation Resistor, RCOMP
See Equation 18
30 kΩ
Compensation Capacitor, CCOMP
See Equation 19
820 pF
CHANNEL 2 CONFIGURATION AND COMPONENTS
SELECTION
Complete the following steps to configure Channel 2:
1.
For a target output voltage (VOUT) of 1.2 V, connect the
V2SET pin through a 4.7 kΩ resistor to GND (see Table 4).
Because one of the fixed output voltage options is chosen,
the feedback pin (FB2) must be directly connected to the
output of Channel 2, VOUT2.
2.
Estimate the duty cycle (D) range. Ideally,
IN
OUT
V
V
D =
Therefore, for an output voltage of 1.2 V and a nominal
input voltage (VIN) of 5.0 V, the nominal duty cycle (DNOM)
is 0.24. Using the maximum input voltage (10% greater than
the nominal, or 5.5 V) results in the minimum duty cycle
(DMIN) of 0.22, whereas using the minimum input voltage
(10% less than the nominal, or 4.5 V) results in the maximum
duty cycle (DMAX) of 0.27.
However, the actual duty cycle will be larger than the
calculated values to compensate for the power losses in the
converter. Therefore, add 5% to 7% to the value calculated
for the maximum load.
The switching frequency (fSW) of 600 kHz, which is chosen
based on the Channel 1 requirements, meets the duty cycle
ranges that were previously calculated. Therefore, this
switching frequency is acceptable.
3.
Select the inductor by using the following equation:
IN
OUT
SW
L
OUT
IN
V
V
f
I
V
V
L
×
×
=
Δ
)
(
In this equation, VIN = 5 V, VOUT = 1.2 V, ΔIL = 0.3 × IL = 0.9 A,
and fSW = 600 kHz, which results in L = 1.67 μH.
Therefore, when L = 2.2 μH (the closest standard value) in
Equation 5, ΔIL = 0.69 A.
Although the maximum output current required is 3 A,
the maximum peak current is 4.5 A for the current-limit
condition (see Table 7). Therefore, the inductor should be
rated for a peak current of 4.5 A and an average current of
3 A for reliable circuit operation in all conditions.
4.
Select the output capacitor by using the following equations:
)
-
(
8
ESR
ΔI
ΔV
f
ΔI
C
L
RIPPLE
SW
L
OUT_MIN
×
×
×
⎟⎟
⎜⎜
×
×
DROOP
SW
OUT_STEP
OUT_MIN
ΔV
f
ΔI
C
3
The first equation is based on the output ripple (ΔVRIPPLE),
whereas the second equation is based on the transient load
performance requirements that allow, in this case, 5% maxi-
mum deviation. As previously mentioned, perform these
calculations and then choose a capacitor based on the larger
calculated capacitor size.
In this case, the following values are used:
ΔIL = 0.69 A
fSW = 600 kHz
ΔVRIPPLE = 12 mV (1% of 1.2 V)
ESR = 3 mΩ (typical for ceramic capacitors)
ΔIOUT_STEP = 1.5 A
ΔVDROOP = 0.06 V (5% of 1.2 V)
The output ripple based calculation dictates that COUT = 20 μF,
whereas the transient load based calculation dictates that
COUT = 125 μF. To meet both requirements, use the latter to
choose a capacitor. As previously mentioned in the Output
Capacitor Selection section, the capacitance value decreases
when dc bias is applied; therefore, select a higher value. In
this case, choose a 47 μF, 6.3 V capacitor and a 100 μF,
6.3 V capacitor in parallel to meet the requirements.



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