ADP2116ACPZ-R7 datasheet(27/36 Pages) AD

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ADP2116

Rev. 0 | Page 27 of 36

To avoid saturation, the rated current of the inductor must be

larger than the maximum peak inductor current, IL_PEAK, given by

MAX

LOAD

PEAK

(6)

where:

ILOAD_MAX is the maximum dc load current.

ΔIL is the peak-to-peak inductor ripple current.

The ADP2116 can be configured in either a 3 A/3 A or 3 A/2 A

current-limit configuration; therefore, the current-limit

thresholds for the two channels are different in each setting.

The inductor chosen for each channel must have at least the

peak output current limit of the IC in each case for robust

operation during short-circuit conditions. The following

inductors are recommended:

•

For 0.47 μH to 4.7 μH, the TOKO D53LC and

FDV0620 series inductors

•

For 4.7 μH to 15 μH, the Cooper Bussmann DR1050 series

and the Würth Elektronik WE-PDF series

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage

ripple and the loop dynamics of the converter. The ADP2116

is designed for operation with small ceramic output capacitors

that have low ESR and low ESL and are, therefore, easily able to

meet stringent output voltage ripple specifications. X5R or X7R

dielectrics are recommended with a voltage rating of 6.3 V or

10 V. Y5V and Z5U dielectrics are not recommended due to their

poor temperature and dc bias characteristics. The minimum

output capacitance, COUT_MIN, is determined by Equation 7 and

Equation 8.

An acceptable maximum output voltage ripple is

⎟

⎠

⎞

⎜

⎝

⎛

≅

OUT_MIN

RIPPLE

ESR

ΔI

ΔV

(7)

Therefore,

)

(

—

ESR

ΔI

ΔV

ΔI

RIPPLE

OUT_MIN

≅

(8)

where:

ΔVRIPPLE is the allowable peak-to-peak output voltage ripple in volts.

ΔIL is the inductor ripple current.

ESR is the equivalent series resistance of the capacitor in ohms.

fSW is the converter switching frequency in hertz.

If there is a step load, choose the output capacitor value based

on the value of the step load. For the maximum acceptable

output voltage droop/overshoot caused by the step load,

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

≅

DROOP

OUT_STEP

OUT_MIN

ΔV

ΔI

(9)

where:

ΔIOUT_STEP is the load step value in amperes.

fSW is the switching frequency in hertz.

ΔVDROOP is the maximum allowable output voltage

droop/overshoot in volts for the load step.

Note that the previous equations are approximations and are

based on the following assumptions:

•

The inductor value is based on the peak-to-peak current

being 30% of the maximum load current.

•

Voltage drops across the internal MOSFET switches and

across the dc resistance of the inductor are ignored.

•

In Equation 9, it is assumed that it takes up to three

switching cycles until the loop adjusts the inductor current

in response to the load step.

Select the largest output capacitance given by Equation 8 and

Equation 9. When choosing the type of ceramic capacitor for

the output filter of the converter, select a capacitor with a nominal

capacitance that is 20% to 30% larger than the calculated value

because the effective capacitance decreases with larger dc voltages.

In addition, the rated voltage of the capacitor must be higher

than the output voltage of the converter.

Recommended input and output ceramic capacitors include

•

Murata GRM21BR61A106KE19L, 10 μF, 10 V, X5R, 0805

•

TDK C2012X5R0J226M, 22 μF, 6.3 V, X5R, 0805

•

Taiyo Yuden JMK212BJ476MG-T, 47 μF, 6.3 V, X5R, 0805

•

Murata GRM32ER60J476ME20L, 47 μF, 6.3 V, X5R, 1210

•

Murata GRM32ER60J107ME20L, 100 μF, 6.3 V, X5R, 1210

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