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ADP2116ACPZ-R7 数据表(PDF) 7 Page - Analog Devices

部件名 ADP2116ACPZ-R7
功能描述  Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2116ACPZ-R7 数据表(HTML) 7 Page - Analog Devices

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ADP2116
Rev. 0 | Page 7 of 36
Pin No.
Mnemonic
Description
14
VIN4
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
15
VIN5
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
16
VIN6
Power Supply Input. The source of the high-side internal power MOSFET of Channel 2.
17
SW4
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
18
SW3
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 2.
Tie SW3 to SW4, and then connect the output LC filter between the switching node and the output voltage.
19
PGND4
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
20
PGND3
Power Ground. The source of the low-side internal power MOSFET of Channel 2.
21
PGND2
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
22
PGND1
Power Ground. The source of the low-side internal power MOSFET of Channel 1.
23
SW2
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
24
SW1
Switch Node Output. The drain of the P-channel power switch and N-channel synchronous rectifier of Channel 1.
Tie SW1 to SW2, and then connect the output LC filter between the switching node and the output voltage.
25
VIN3
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
26
VIN2
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
27
VIN1
Power Supply Input. The source of the high-side internal power MOSFET of Channel 1.
28
EN1
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 converter; drive EN1 low to turn off the Channel 1
converter. Tie EN1 to VDD for startup with VDD. When using a multiphase configuration, connect EN1 to EN2.
29
PGOOD1
Open-Drain Power-Good Output for Channel 1. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is
5.5 V or less; PGOOD1 is held low when Channel 1 is out of regulation.
30
SS1
Soft Start Input for Channel 1. Place a capacitor from SS1 to GND to set the soft start period. A 10 nF capacitor
sets a 1 ms soft start period. For multiphase configuration, connect SS1 to SS2.
31
V1SET
Output Voltage Set Pin for Channel 1. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)
for VOUT1, connect this pin through a resistor to GND (see Table 4 for details). To select an adjustable output voltage
for VOUT1, connect this pin to GND through an 82 kΩ resistor or tie this pin directly to VDD depending on the
output voltage desired.
32
FB1
Feedback Voltage Input for Channel 1. For the fixed output voltage option, connect FB1 to VOUT1. For the adjustable
output voltage option, connect this pin to a resistor divider between VOUT1 and GND. With multiphase
configurations, the FB1 and FB2 pins should be tied together and then connected to VOUT.
EP
Exposed Thermal Pad. Connect the exposed thermal pad to the signal/analog ground plane.



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