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ADP2116ACPZ-R7 数据表(PDF) 16 Page - Analog Devices

部件名 ADP2116ACPZ-R7
功能描述  Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2116ACPZ-R7 数据表(HTML) 16 Page - Analog Devices

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ADP2116
Rev. 0 | Page 16 of 36
CH3 5.0V
CH2 1.0V
CH4 2.0A
M10.0µs 1.25GS/s A CH2
1.12V
2
3
4
SW3, SW4
IT 200ps/pt
Ω
B
W
B
W
B
W
VOUT2
INDUCTOR CURRENT
Figure 47. Current Limit Entry (Zoomed In),
Channel 2: VOUT2 = 1.8 V, 2 A Configuration, fSW = 600 kHz
CH3 5.0V
CH2 1.0V
CH4 2.0A
M2.0ms 5.0MS/s A CH4
1.72A
2
3
4
SW3, SW4
200ns/pt
Ω
B
W
B
W
B
W
VOUT2
INDUCTOR CURRENT
Figure 48. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle
CH3 5.0V
CH2 1.0V
CH4 2.0A
M2.0ms 1.25GS/s A CH2
1.12V
2
3
4
SW3, SW4
IT 40ns/pt
B
W
Ω
B
W
B
W
INDUCTOR CURRENT
VOUT2
Figure 49. Exiting Hiccup Mode, Channel 2: VOUT2 = 1.8 V, fSW = 600 kHz
CH3 5.0V
CH1 5.0V
CH4 5.0V
M1.0µs 1.25GS/s
IT 100ps/pt
A CH1
3.0V
4
3
1
B
W
B
W
B
W
EXTERNAL SYNC
CHANNEL 2 SW
CHANNEL 1 SW
Figure 50. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz
CH3 5.0V
CH1 5.0V
CH4 5.0V
M1.0µs 1.25GS/s
A CH4
3.0V
3
1
4
IT 100psns/pt
B
W
B
W
B
W
INTERNAL CLKOUT
CHANNEL 2 SW
CHANNEL 1 SW
Figure 51. Internal Clock Output, fSW = 600 kHz, fCLKOUT = 1.2 MHz
CH3 2.0V
CH1 2.0V
CH2 2.0V
CH4 2.0V
M1.0µs 1.25GS/s
A CH1
2.0V
2
3
4
1
CHANNEL 1 SW
CHANNEL 3 SW
CHANNEL 2 SW
CHANNEL 4 SW
IT 400ps/pt
B
W
B
W
B
W
B
W
Figure 52. 4-Channel Operation, Two ADP2116 Devices, One Device
Synchronizes the Other, 90° Phase-Shifted Switch Nodes



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