ADP2116

Rev. 0 | Page 6 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

GND

2

COMP1

3

FREQ

4

SCFG

5

SYNC/CLKOUT

6

OPCFG

7

COMP2

8

VDD

24 SW1

23 SW2

22 PGND1

21 PGND2

20 PGND3

19 PGND4

18 SW3

17 SW4

TOP VIEW

(Not to Scale)

ADP2116

THERMAL PAD

NOTES

1. CONNECT THE EXPOSED THERMAL PAD TO THE

SIGNAL/ANALOG GROUND PLANE.

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Ground for the Internal Analog and Digital Circuits. Connect GND to the signal/analog ground plane before connecting

to the power ground.

2

COMP1

Error Amplifier Output for Channel 1. Connect a series RC network from COMP1 to GND to compensate the control

loop of Channel 1. For multiphase operation, tie COMP1 and COMP2 together.

3

FREQ

Frequency Select Input. Connect this pin through a resistor to GND to set the appropriate switching frequency

(see Table 5).

4

SCFG

Synchronization Configuration Input. SCFG configures the SYNC/CLKOUT pin as an input or output. Tie this pin to

VDD to configure SYNC/CLKOUT as an output. Tie this pin to GND to configure SYNC/CLKOUT as an input.

5

SYNC/CLKOUT

External Synchronization Input/Internal Clock Output. This bidirectional pin is configured with the SCFG pin (see the

Pin 4 description for details). When this pin is configured as an output, a buffered clock of twice the switching frequency

with a phase shift of 90° is available on this pin. When configured as an input, this pin accepts an external clock to which

the converters are synchronized. The frequency select resistor, mentioned in the description of Pin 3, must be selected

to be close to the expected switching frequency for stable operation (see the Setting the Oscillator Frequency section).

6

OPCFG

Operation Configuration Input. Connect this pin to VDD or through a resistor to GND to set the system mode of

operation according to Table 7. This pin can be used to select a peak current limit for each power channel and to

enable or disable the pulse skip mode.

7

COMP2

Error Amplifier Output for Channel 2. Connect a series RC network from COMP2 to GND to compensate the control

loop of Channel 2. For multiphase operation, tie COMP1 and COMP2 together.

8

VDD

Power Supply Input. The power source for the ADP2116 internal circuitry. Connect VDD and VINx with a 10 Ω resistor

as close as possible to the ADP2116. Bypass VDD to GND with a 1 μF or greater capacitor.

9

FB2

adjustable output voltage option is 0.6 V. With multiphase configurations, the FB2 and FB1 pins should be tied

10

V2SET

Output Voltage Set Pin for Channel 2. To select a fixed output voltage option (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V)

output voltage desired.

11

SS2

Soft Start Input for Channel 2. Place a capacitor from SS2 to GND to set the soft start period. A 10 nF capacitor

sets a 1 ms soft start period. For multiphase configuration, connect SS2 to SS1.

12

PGOOD2

Open-Drain Power-Good Output for Channel 2. Place a 100 kΩ pull-up resistor to VDD or to any other voltage that is

5.5 V or less; PGOOD2 is held low when Channel 2 is out of regulation.

13

EN2

Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 converter; drive EN2 low to turn off the Channel 2

converter. Tie EN2 to VDD for startup with VDD. When using a multiphase configuration, connect EN2 to EN1.