ADP2116ACPZ-R7 datasheet(21/36 Pages) AD

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ADP2116

Rev. 0 | Page 21 of 36

The capacitance value of the soft start capacitor defines the soft

start time, tSS, based on

REF

(1)

where:

VREF is the internal reference voltage, 0.6 V.

ISS is the soft start current, 6 μA.

CSS is the soft start capacitor value.

If the output voltage, VOUT1 or VOUT2, is precharged prior to enabling

Channel 1 or Channel 2, respectively, the control logic prevents

inductor current reversal by keeping the power MOSFETs turned

off until the soft start voltage ramp at SS1 or SS2 reaches the

precharged output voltage on VFB1 or VFB2 (see Figure 59).

CH3 5.0V

CH2 1.0V

CH1 5.0V

CH4 500mV

M200µs 50MS/s

A CH1

2.4V

EN1

VOUT1

SS1

SW1, SW2

20ns/pt

Figure 59. Soft Start with a Precharged Output

POWER GOOD

The ADP2116 features open-drain power-good outputs (PGOOD1

and PGOOD2) that indicate when the converter output voltage

is within regulation. The power-good signal transitions low

immediately when the corresponding channel is disabled.

The power-good circuitry monitors the output voltage on the FB1

or FB2 pin and compares it to the rising and falling thresholds

specified in Table 1. If the rising output voltage (VOUT1 or VOUT2)

exceeds 116% of the target output voltage (VOUT1SET or VOUT2SET),

the PGOOD1 or PGOOD2 pin is held low. The PGOOD1 or

PGOOD2 pin continues to be held low until the falling output

voltage returns to 108% of the target value.

If the output voltage drops below 84% of the target output voltage,

the corresponding PGOOD1 or PGOOD2 pin is held low. The

PGOOD1 or PGOOD2 pin continues to be held low until the

output voltage rises to within 92% of the target output voltage.

The PGOOD1 or PGOOD2 pin is then released, signaling that

the output voltage is within the power-good window.

The power-good thresholds are shown in Figure 60. The PGOOD1

and PGOOD2 outputs also sink current if an overtemperature

condition is detected. Use these outputs as logic power-good

signals by connecting the pull-up resistor from PGOOD1 or

PGOOD2 to VDD. If the power-good function is not used, the

pins can be left floating.

PULSE SKIP MODE

The ADP2116 has built-in pulse skip circuitry that turns on

during light loads, switching only as necessary to maintain the

output voltage within regulation. This allows the converter to

maintain high efficiency during light load operation by reducing

the switching losses. The pulse skip mode can be selected by

configuring the OPCFG pin as indicated in Table 7. In pulse

skip mode, when the output voltage dips below regulation, the

ADP2116 enters PWM mode for a few oscillator cycles to increase

the output voltage so that it is within regulation. During the wait

time between bursts, both power switches are off, and the output

capacitor supplies all of the load current. Because the output voltage

dips and recovers occasionally, the output voltage ripple in this

mode is larger than the ripple in the PWM mode of operation.

If the converter is configured to operate in forced PWM mode

(by selecting this configuration using the OPCFG pin), the device

operates with a fixed switching frequency, even at light loads.

108%

92%

116%

84%

100%

PGOOD1/PGOOD2

VOUT FALLING

VOUT RISING

POWER

GOOD

OVERVOLTAGE

UNDERVOLTAGE

POWER

GOOD

Figure 60. PGOOD1/PGOOD2 Thresholds

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