DM9013 datasheet(5/75 Pages) DAVICOM

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DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

6.41 Per Port Control/Status Index Register (60H)........................................................................................... 28

6.42 Per Port Control Data Register (61H) ........................................................................................................ 28

6.43 Per Port Status Data Register (62H) .......................................................................................................... 29

6.44 Per Port Forward Control Register (65H) .................................................................................................. 29

6.45 Per Port Ingress/Egress Control Register (66H) ...................................................................................... 30

6.46 Bandwidth Control Setting Register (67H)................................................................................................ 31

6.47 Per Port Block Unicast ports Control Register (68H) .............................................................................. 31

6.48 Per Port Block Multicast ports Control Register (69H)............................................................................ 31

6.49 Per Port Block Broadcast ports Control Register (6AH) ......................................................................... 31

6.50 Per Port Block Unknown ports Control Register (6BH) .......................................................................... 32

6.51 Per Port Priority Queue Control Register (6DH)....................................................................................... 32

6.52 Per Port VLAN Tag Low Byte Register (6EH) ........................................................................................... 32

6.53 Per Port VLAN Tag High Byte Register (6FH)........................................................................................... 32

6.54 MIB counter Port Index Register (80H)...................................................................................................... 32

6.55 MIB counter Data Register (81H~84H)....................................................................................................... 32

6.56 Port-based VLAN mapping table Registers (B0H~BFH)..........................................................................33

6.57 TOS Priority Map Registers (C0H~CFH).................................................................................................... 33

6.58 VLAN Priority Map Registers (D0H~D1H) ................................................................................................. 36

6.59 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ........................ 36

6.60 Memory Data Read Command with Address Increment Register (F2H)................................................ 36

DM9013 数据表(PDF) 5 Page - Davicom Semiconductor, Inc.

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