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DM9013 数据表(PDF) 16 Page - Davicom Semiconductor, Inc. |
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DM9013 数据表(HTML) 16 Page - Davicom Semiconductor, Inc. |
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16 / 75 page ![]() DM9013 3-port switch with Processor Interface 16 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 5.6 Clock Interface Pin No. Pin Name I/O Description 101 X1 I Crystal 25MHz In 102 X2 O Crystal 25MHz Out 116 SCLK I External system clock source 5.7 Network Interface Pin No. Pin Name I/O Description 80,81 TX1+/- I/O Port 1 TP TX 84,85 RX1+/- I/O Port 1 TP RX 88,89 TX0+/- I/O Port 0 TP TX 92,93 RX0+/- I/O Port 0 TP RX 95 BGRES I/O Band gap Pin 96 BGGND P Band gap Ground 97 VCNTL I/O 1.8V Voltage control 98 VREF O Voltage Reference 5.8 Miscellaneous Pins Pin No. Pin Name I/O Description 53 PWRST# I Power on Reset. 76 TEST1 I,PD Tie to ground in application 77 TEST2 I,PD 0: 3-port mode All ports are active in this mode. 1: 2-port mode Only 2 ports are active in this mode. Port 1 or port 2 can be disabled by strap TXEN2. In this mode, the disabled port’s memory resource is shared by processor port and the other 2 ports. 78 TEST3 I,PD Tie to ground in application 5.9 Power Pins Pin No. Pin Name I/O Description 4,18,32,40,48,62,75,100 VCC3 P Digital 3.3V 24,57,120 VCCI P Internal 1.8V core power 11,21,27,35,45, 54,69,103,125 GND P Digital GND 86,94,99 AVDD3 P Analog 3.3V power 79,87 AVDDI P Analog 1.8V power 82,83,90,91 AGND P Analog GND |
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