DM9013 datasheet(52/75 Pages) DAVICOM

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DM9013

3-port switch with Processor Interface

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

8.12 (Specified config) Register – 14H

Bit

Bit Name

Default

Description

TSTSE1

0,RW

Vendor test select control

TSTSE2

0,RW

Vendor test select control

FORCE_TXSD

0,RW

Force Signal Detect

0: normal SD signal.

1: force SD signal OK in 100M

FORCE_FEF

0,RW

Vendor test select control

PREAMBLEX

0,RW

Preamble Saving Control

0: when bit 10 is set, the 10M TX preamble count is reduced.

When bit 11 of register 29 is set, 12-bit preamble bit is

reduced;

otherwise 22-bit preamble bits is reduced.

1: 10M TX preamble bit count is normal.

TX10M_PWR

1,RW

10M TX Power Saving Control

1: enable 10M TX power saving

0: disable 10M TX power saving

NWAY_PWR

0,RW

N-Way Power Saving Control

1: disable N-Way power saving

0: enable N-Way power saving

Reserved

0, RO

Reserved

Read as 0, ignore on write

MDIX_CNTL

MDI/MDIX,RO The polarity of MDI/MDIX value

0: MDI mode

1: MDIX mode

AutoNeg_dpbk

0,RW

Auto-negotiation Loopback

0: normal.

1: test internal digital auto-negotiation Loopback

Mdix_fix Value

0, RW

MDIX_CNTL force value:

When Mdix_down = 1, MDIX_CNTL value depend on the register

value.

Mdix_down

0,RW

MDIX Down

Manual force MDI/MDIX.

0: Enable HP Auto-MDIX

1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5

MonSel1

0,RW

Vendor monitor select

MonSel0

0,RW

Vendor monitor select

Reserved

0,RW

Reserved

Force to 0, in application.

PD_value

0,RW

Power down control value

Decision the value of each field Register 19.

0: normal

1: power down

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