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DM9013 数据表(PDF) 22 Page - Davicom Semiconductor, Inc. |
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DM9013 数据表(HTML) 22 Page - Davicom Semiconductor, Inc. |
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22 / 75 page  DM9013 3-port switch with Processor Interface 22 Preliminary datasheet DM9013-15-DS-P03 April 9, 2009 6.5 RX Status Register (06H) Bit Name Default Description 7:4 RESERVED 0,RO Reserved 3:2 SRCP 0,RO Source Port Number 1 CE PH0,RO CRC Error It is set to indicate that the received frame ends with a CRC error 0 RESERVED 0,RO Reserved 6.6 Receive Overflow Counter Register (07H) Bit Name Default Description 7 RXFU PHS0,R/C Receive Overflow Counter Overflow This bit is set when the ROC has an overflow condition 6:0 ROC PHS0,R/C Receive Overflow Counter This is a statistic counter to indicate the received packet count upon FIFO overflow 6.7 Flow Control Register (0AH) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 FLOW_EN PHS0,RW RX Flow Control Enable Enables the pause packet for high/low water threshold control 4:0 RESERVED 0,RO Reserved 6.8 EEPROM & PHY Control Register (0BH) Bit Name Default Description 7:6 RESERVED 0,RO Reserved 5 REEP PH0,RW Reload EEPROM. Driver needs to clear it up after the operation completes 4 WEP PH0,RW Write EEPROM Enable 3 EPOS PH0,RW EEPROM or PHY Operation Select When reset, select EEPROM; when set, select PHY 2 ERPRR PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after the operation completes. 1 ERPRW PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after the operation completes. 0 ERRE PH0,RO EEPROM Access Status or PHY Access Status When set, it indicates that the EEPROM or PHY access is in progress 6.9 EEPROM & PHY Address Register (0CH) Bit Name Default Description 7:6 PHY_ADR PH01,RW PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0. 5:0 EROA PH0,RW EEPROM Word Address or PHY Register Address 6.10 EPROM & PHY Data Register (0DH~0EH) Bit Name Default Description 7:0 EE_PHY_L PH0,RW EEPROM or PHY Low Byte Data (0DH) This data is made to write low byte of word address defined in Reg. CH to EEPROM or PHY 7:0 EE_PHY_H PH0,RW EEPROM or PHY High Byte Data (0EH) This data is made to write high byte of word address defined in Reg. CH to EEPROM or PHY |
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