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DM9013 数据表(PDF) 24 Page - Davicom Semiconductor, Inc.

部件名 DM9013
功能描述  10/100 Mbps 3-port Ethernet Switch Controller with General Processor Interface
PDF  75 Pages
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制造商  DAVICOM [Davicom Semiconductor, Inc.]
网页  http://www.davicom.com.tw
标志 DAVICOM - Davicom Semiconductor, Inc.

DM9013 数据表(HTML) 24 Page - Davicom Semiconductor, Inc.

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DM9013
3-port switch with Processor Interface
24
Preliminary datasheet
DM9013-15-DS-P03
April 9, 2009
6.17 RX Additional Status Register ( 26H )
Bit
Name
Default
Description
7:4
RESERVED
0,RO
Reserved
1:0
RPTRS
PH,RO
uP received pointer status, only available when RX pointer restriction is enabled
( Reg27h.7=0).
00: Within buffer
01: End of buffer
1x: Exceed buffer
6.18 RX Additional Control Register ( 27H )
Bit
Name
Default
Description
7
RPRD
PHS0,RW
RX pointer restriction disable
6:0
RESERVED
0,RO
Reserved
6.19 Vendor ID Register (28H~29H)
Bit
Name
Default
Description
7:0
VIDH
PE,0AH,RO
Vendor ID High Byte (29H)
7:0
VIDL
PE,46H.RO
Vendor ID Low Byte (28H)
6.20 Product ID Register (2AH~2BH)
Bit
Name
Default
Description
7:0
PIDH
PE,90H,RO
Product ID High Byte (2BH)
7:0
PIDL
PE,13H.RO
Product ID Low Byte (2AH)
6.21 Chip Revision Register (2CH)
Bit
Name
Default
Description
7:0
CHIPR
P01H,RO
CHIP Revision
6.22 Transmit Control Register 2 (2DH)
Bit
Name
Default
Description
7
RESERVED
0,RW
Reserved, Clear to 0 in application.
6:5
RESERVED
0,RO
Reserved
4
ONEPM
P0,RW
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
3:0
RESERVED
0,RO
Reserved
6.23 Transmit Check Sum Control Register (31H)
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
HP0,RW
UDP Checksum Generation Enable
1
TCPCSE
HP0,RW
TCP Checksum Generation Enable
0
IPCSE
HP0,RW
IP Checksum Generation Enable



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