CS4294SLASHCS4298 datasheet(45/66 Pages) CIRRUS

45 / 66 page

CS4202

DS549PP2

8. POWER MANAGEMENT

8.1

AC ’97 Reset Modes

The CS4202 supports four reset methods, as de-

fined in the AC ’97 Specification: Cold Reset,

Warm Reset, New Warm Reset, and Register Reset.

A Cold Reset results in all AC ’97 logic (registers

included) initialized to its default state. A Warm

Reset or New Warm Reset leaves the contents of

the AC ’97 register set unaltered. A Register Reset

initializes only the AC ’97 registers to their default

states.

8.1.1

Cold Reset

A Cold Reset is achieved by asserting RESET# for

a minimum of 1 µs after the power supply rails

have stabilized. This is done in accordance with the

minimum timing specifications in the AC ’97 Seri-

al Port Timing section on page 9. Once de-asserted,

all of the CS4202 registers will be reset to their de-

fault power-on states and the BIT_CLK and

SDATA_IN signals will be reactivated.

8.1.2

Warm Reset

A Warm Reset allows the AC-link to be reactivated

without losing information in the CS4202 registers.

A Warm Reset is required to resume from a D3hot

state where the AC-link had been halted yet full

power had been maintained. A primary codec

Warm Reset is initiated when the SYNC signal is

driven high for at least 1 µs and then driven low in

the absence of the BIT_CLK clock signal. The

BIT_CLK clock will not restart until at least 2 nor-

mal BIT_CLK clock periods (162.8 ns) after the

SYNC signal is de-asserted. A Warm Reset of the

secondary codec is recognized when the primary

codec on the AC-link resumes BIT_CLK genera-

tion. The CS4202 will wait for BIT_CLK to be sta-

ble to restore SDATA_IN activity, S/PDIF and/or

serial data port transmission on the following

frame.

8.1.3

New Warm Reset

The New Warm Reset also allows the AC-link to

be reactivated without losing information in the

registers. A New Warm Reset is required to resume

from a D3cold state where AC-link power has been

removed. New Warm Reset is recognized by the

low-high transition of RESET# after the AC-link

has been programmed into PR4 powerdown. The

New Warm Reset functionality can be disabled by

setting the CRST bit in the Misc. Crystal Control

8.1.4

The last reset mode provides a Register Reset to the

CS4202. This is available only when the CS4202

AC-link is active and the Codec Ready bit is ‘set’.

The audio (including extended audio) control reg-

isters (Index 00h - 3Ah) and the vendor specific

registers (Index 5Ah - 7Ah) are reset to their de-

fault states by a write of any value to the Reset Reg-

ister (Index 00h). The modem (including GPIO)

registers (Index 3Ch - 56h) are reset to their default

states by a write of any value to the Extended Mo-

dem ID Register (Index 3Ch).

CS4294/CS4298 数据表(PDF) 45 Page - Cirrus Logic

CS4294/CS4298 数据表(HTML) 45 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载