CS4294SLASHCS4298 datasheet(48/66 Pages) CIRRUS

48 / 66 page

CS4202

DS549PP2

9. CLOCKING

The CS4202 may be operated as a primary or sec-

ondary codec. As a primary codec, the system clock

for the AC-link may be generated from an external

24.576 MHz clock source, a 24.576 MHz crystal, or

the internal Phase Locked Loop (PLL). The PLL al-

lows the CS4202 to accept external clock frequen-

cies other than 24.576 MHz. As a secondary codec,

the system clock is derived from BIT_CLK, which is

generated by the primary codec. The CS4202 uses

the presence or absence of a valid clock on the

XTL_IN pin in conjunction with the state of the

ID[1:0]# pins to determine the clocking configura-

tion. See Table 18 for all available CS4202 clocking

modes.

9.1

PLL Operation (External Clock)

The PLL mode is activated if a valid clock is present

on XTL_IN before the rising edge of RESET#. Once

PLL mode is entered, the XTL_OUT pin is redefined

as the PLL loop filter, as shown in Figure 16. The

ID[1:0]# inputs determine the configuration of the

internal divider ratios required to generate the

12.288 MHz BIT_CLK output; see Table 18 on

page 49 for additional details. In PLL mode, the

CS4202 is configured as a primary codec indepen-

dent of the state of the ID[1:0]# pins. If 24.576 MHz

is chosen as the external clock input (ID[1:0]# inputs

both pulled high or left floating), the PLL is disabled

and the clock is used directly. The loop filter is not

required and XTL_OUT is left unconnected. For all

other clock input choices, the loop filter is required.

The ID[1:0] bits of the Extended Audio ID Register

(Index 28h) and the Extended Modem ID Register

(Index 3Ch) will always report ‘00’ in PLL mode.

9.2

24.576 MHz Crystal Operation

If a valid clock is not present on XTL_IN during the

rising edge of RESET#, the device disables the PLL

input and latches the state of the ID[1:0]# inputs. If

the ID[1:0]# inputs are both pulled high or left float-

ing, the device is configured as a primary codec. An

external 24.576 MHz crystal is used as the system

clock as shown in Figure 17.

9.3

Secondary Codec Operation

If a valid clock is not present on XTL_IN and either

ID[1:0]# input is pulled low during the rising edge of

RESET#, the device is determined to be a secondary

codec. The BIT_CLK pin is configured as an input

and the CS4202 is driven from the 12.288 MHz

BIT_CLK of the primary codec. The ID[1:0] bits of

the Extended Audio ID Register (Index 28h) and the

Extended Modem ID Register (Index 3Ch) will re-

port the state of the ID[1:0]# inputs.

Figure 16. PLL External Loop Filter

XTL_OUT

XTL_IN

2.2 k

Ω

0.022 uF

220 pF

Clock Source

DGND

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