CS4294SLASHCS4298 datasheet(18/66 Pages) CIRRUS

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CS4202

DS549PP2

3.2

AC-Link Serial Data Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4202 to the AC ’97 con-

troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 15 illus-

trates the serial port timing.

The PCM capture data from the CS4202 is shifted out MSB first in the most significant 18 bits of each slot.

The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97

Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun-

cate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4202 will always be returned ‘cleared’.

3.2.1

Serial Data Input Slot Tag Bits (Slot 0)

Codec Ready

Codec Ready. The Codec Ready bit indicates the readiness of the CS4202 AC-link. Immedi-

ately after a Cold Reset this bit will be ‘clear’. Once the CS4202 clocks and voltages are sta-

ble, this bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be

attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs,

ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Con-

trol/Status Register (Index 26h) by the controller before any access is made to the mixer reg-

isters. Any accesses to the CS4202 while Codec Ready is ‘clear’ are ignored.

Slot 1 Valid

The Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid

The Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:4,6:8,11] Valid The Slot [3:4,6:8,11] Valid bits indicate Slot [3:4,6:8,11] contains valid capture data from the

CS4202 ADCs. If a bit is ‘set’, the corresponding input slot contains valid data. If a bit is

‘cleared’, the corresponding slot will be ignored.

Slot 12 Valid

The Slot 12 Valid bit indicates Slot 12 contains valid GPIO status data.

3.2.2

Status Address Port (Slot 1)

RI[6:0]

been requested in the previous frame. The CS4202 will only echo the register index for a read

access. Write accesses will not return valid data in Slot 1.

SR[3:4,6:11]

Slot Request. If SRx is ‘set’, this indicates the CS4202 SRC does not need a new sample on

the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample

is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register

(Index 2Ah) is ‘clear’, the SR[3:4,6:11] bits are always 0. When VRA is ‘set’, the SRC is en-

abled and the SR[3:4,6:11] bits are used to request data.

Bit 15

654

3210

Codec

Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 11

Valid

Slot 12

Valid

Reserved

Bit 19

98765432

Res

RI6

RI5

RI4

RI3

RI2

RI1

RI0

SR3 SR4

SR6 SR7 SR8 SR9 SR10 SR11

Reserved

CS4294/CS4298 数据表(PDF) 18 Page - Cirrus Logic

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