CS4294SLASHCS4298 datasheet(59/66 Pages) CIRRUS

59 / 66 page

CS4202

DS549PP2

AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29

This pin needs a 1000 pF NPO capacitor connected to analog ground.

AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30

This pin needs a 1000 pF NPO capacitor connected to analog ground.

HPCFG - Headphone Configuration, Input, Pin 31

This pin is the configuration control for the signal routing to the headphone amplifier. If this pin is left

floating, the LINE_OUT and HP_OUT pins function as defined in the AC ’97 specification. If the HPCFG

pin is grounded, the HP_OUT pins behave as a buffered line output. In addition, the LINE_OUT pins are

muted, the control register for the headphone output will be the Master Output Volume Register (Index

02h), and PC_BEEP is routed to the HP_OUT pins during RESET. The HPCFG pin is internally pulled

up to the analog supply voltage.

AC-Link Pins

RESET# - AC ’97 Chip Reset, Input, Pin 11

This active low signal is the asynchronous Cold Reset input to the CS4202. The CS4202 must be reset

before it can enter normal operating mode.

SYNC - AC-Link Serial Port Sync Pulse, Input, Pin 10

SYNC is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample

rate, 48 kHz. The signal is generated by the controller and is synchronous to BIT_CLK. SYNC is an

asynchronous input when the CS4202 is configured as a primary codec and is in a PR4 powerdown

state. A series terminating resistor of 47

Ω should be connected on this signal close to the controller.

BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6

This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a

12.288 MHz output clock derived from either a 24.576 MHz crystal or from the internal PLL based on

the XTL_IN input clock. When the CS4202 is in secondary mode, this signal is an input which controls

the AC-link serial interface and generates all internal clocking including the AC-link serial interface

timing and the analog sampling clocks. A series terminating resistor of 47

Ω should be connected on

this signal close to the CS4202 in primary mode or close to the BIT_CLK source in secondary mode.

SDATA_OUT - AC-Link Serial Data Input Stream to AC ’97, Input, Pin 5

This input signal receives the control information and digital audio output streams. The data is clocked

into the CS4202 on the falling edge of BIT_CLK. A series terminating resistor of 47

Ω should be

connected on this signal close to the controller.

SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8

This output signal transmits the status information and digital audio input streams from the ADCs. The

data is clocked out of the CS4202 on the rising edge of BIT_CLK. A series terminating resistor of 47

Ω

should be connected on this signal close to the CS4202.

CS4294/CS4298 数据表(PDF) 59 Page - Cirrus Logic

CS4294/CS4298 数据表(HTML) 59 Page - Cirrus Logic

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