STA015 datasheet(12/56 Pages) STMICROELECTRONICS

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3.4 ADC Inteface

Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input

interface is also available, suitable to interface with most A/D converters. To configure this interface 4 spe-

cific I2C registers are available (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to

registers description for more details.

3.5 General Purpose I/O Interface

A new general purpose I/O interface has been added to this device (TQFP44 and LFBGA64 only). Actually

only the strobe line is used in ADPCM encoding mode to provide an interrupt; other pins are reserved for

future use. The related configuration register is GPIO_CONF. See the following summary for related pin

usage:

4.0 ADPCM ENCODING: OVERVIEW

According to the previously described interfaces there are 4 ways to manage ADPCM data stream while

encoding. Input interface can be either the serial receiver block (SDI + SCKR + DATA_REQ lines) or the

ADC specific interface.

Output interfaces can be either the I2C bus (with or without interrupt line) or the GPSO high-speed serial

interface (GPSO_REQ + GPSO_ DATA + GPSO_SCKR lines). This result in the following 4 methods to

handle encoding flow:

(*) STA013 Compatible mode

Figure 10.

Name

Description

Dir

I/ODATA [0]

..................

I/ODATA [7]

GPIO data line

I/O

.....

I/O

GPIO_STROBE

GPIO strobe line

I/O

INPUT (data to encode)

Output (encoded data)

Available on package

ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)

GPSO I/F (GPSO_REQ + GPSO_DATA +

GPSO_SCKR)

TQFP44/LFBGA64

ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)

I2C + Interrupt (SCL + SDA +DATA_REQ)

SO28/TQFP44

LFBGA64

SERIAL I/F (SCKR + SDI + DATA_REQ)

GPSO I/F (GPSO_REQ + GPSO_DATA +

GPSO_SCKR)

TQFP44/LFBGA64

SERIAL I/F (SCKR + SDI + DATA_REQ) (*)

I2C (polling) (SCL + SDA)

SO28/TQFP44

LFBGA64

STA015

MCU

GPSO_SCKR

GPSO_REQ

GPSO_DATA

GPSO_REQ

D00AU1145

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