STA015 datasheet(49/56 Pages) STMICROELECTRONICS

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STA015

Table 2.

PLL Configuration Sequence For

10MHz Input Clock

256 Oversapling Clock

Table 3.

PLL Configuration Sequence For

10MHz Input Clock

384 Oversapling Rathio

Table 4.

PLL Configuration Sequence For

14.31818MHz Input Clock

256 Oversapling Rathio

Table 5.

PLL Configuration Sequence For

14.31818MHz Input Clock

384 Oversapling Rathio

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

169

PLLFRAC-441-H

100

PLLFRAC-L

PLLFRAC-441-L

5PLLCTRL

161

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

110

PLLFRAC-441-H

160

100

PLLFRAC-L

152

PLLFRAC-441-L

186

5PLLCTRL

161

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

187

PLLFRAC-441-H

103

100

PLLFRAC-L

PLLFRAC-441-L

119

PLLCTRL

161

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

PLLFRAC-441-H

157

100

PLLFRAC-L

211

PLLFRAC-441-L

157

PLLCTRL

161

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