STA015 datasheet(16/56 Pages) STMICROELECTRONICS

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5.4 READ OPERATION (see Fig. 17)

5.4.1 Current byte address read

The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is in-

cremented. For the current byte address read mode, following a START condition the master sends the

device address with the RW bit set to 1.

The STA015 acknowledges this and outputs the byte addressed by the internal byte address counter. The

master does not acknowledge the received byte, but terminates the transfer with a STOP condition.

5.4.2 Sequential address read

This mode can be initiated with either a current address read or a random address read. However in this

case the master does acknowledge the data byte output and the STA015 continues to output the next byte

in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte,

but terminates the transfer with a STOP condition. The output data stream is from consecutive byte ad-

dresses, with the internal byte address counter automatically incremented after one byte output.

6.0 I2C REGISTERS

The following table gives a description of the MPEG Source Decoder (STA015) register list.

The first column (HEX_COD) is the hexadecimal code for the sub-address.

The second column (DEC_COD) is the decimal code.

The third column (DESCRIPTION) is the description of the information contained in the register.

The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default

is "undefined".

The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful

size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits

only.

I2C REGISTERS

HEX_COD

DEC_COD

DESCRIPTION

RESET

R/W

$00

VERSION

R (8)

$01

IDENT

0xAC

R (8)

$05

PLLCTL [7:0]

0xA1

R/W (8)

$06

PLLCTL [20:16] (MF[4:0]=M)

0x0C

R/W (8)

$07

PLLCTL [15:12] (IDF[3:0]=N)

0x00

R/W (8)

$0C

REQ_POL

0x01

R/W (8)

$0D

SCLK_POL

0x04

R/W (8)

$0F

ERROR_CODE

0x00

R (8)

$10

SOFT_RESET

0x00

W (8)

$13

PLAY

0x01

R/W(8)

$14

MUTE

0x00

R/W(8)

$16

CMD_INTERRUPT

0x00

R/W(8)

$18

DATA_REQ_ENABLE

0x00

R/W(8)

$40 - $51

64 - 81

ADPCM_DATA_1 to ADPCM_DATA_18

0x00

R (8)

$40

SYNCSTATUS

0x00

R (8)

$41

ANCCOUNT_L

0x00

R (8)

$42

ANCCOUNT_H

0x00

R (8)

$43

HEAD_H[23:16]

0x00

R(8)

$44

HEAD_M[15:8]

0x00

R(8)

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