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STA015 数据表(PDF) 19 Page - STMicroelectronics

部件名 STA015
功能描述  MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
PDF  56 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA015 数据表(HTML) 19 Page - STMicroelectronics

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STA015
UPD_FRAC: when is set to 1, update FRAC in the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, use the XTI as input of the divider X instead of VCO output. It is set to 0 on
HW reset.
XTI2DSPCLK: when is to 1, set use the XTI as input of the divider S instead of VCO output. It is set to 0
on HW reset.
PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing.
It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28 (OUT_CLOCK/DATA_REQ) is enabled. It is set to 0 after
autoboot.
PLLCTL (M)
Address: 0x06 (06)
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL (N)
Address: 0x07 (07)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the STA015 PLL by DSP embedded software.
M and N registers are R/W type but they are completely controlled, on STA015, by DSP software.
REQ_POL
Address: 0x0C (12)
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
The REQ_POL registers is used to program the polarity of the DATA_REQ line.
Default polarity (the source sends data when the DATA_REQ line is high)
Inverted polarity (the source sends data when the ATA_REQ line is low)
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
00
0000
01
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
00
0001
01



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