STA015 datasheet(50/56 Pages) STMICROELECTRONICS

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Table 6.

PLL Configuration Sequence For

14.31818MHz Input Clock

512 Oversapling Rathio

Table 7.

PLL Configuration Sequence For

14.7456MHz Input Clock

256 Oversapling Rathio

Table 8.

PLL Configuration Sequence For

14.7456MHz Input Clock

384 Oversapling Rathio

Table 9.

PLL Configuration Sequence For

14.7456MHz Input Clock

512 Oversapling Rathio

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

PLLFRAC-441-H

157

100

PLLFRAC-L

211

PLLFRAC-441-L

157

PLLCTRL

161

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

PLLFRAC-441-H

100

PLLFRAC-L

PLLFRAC-441-L

PLLCTRL

161

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

PLLFRAC-441-H

124

100

PLLFRAC-L

PLLFRAC-441-L

PLLCTRL

161

ADDRESS

NAME

VALUE

reserved

MFSDF (x)

MFSDF-441

101

PLLFRAC-H

PLLFRAC-441-H

184

100

PLLFRAC-L

PLLFRAC-441-L

PLLCTRL

161

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