STA015 datasheet(30/56 Pages) STMICROELECTRONICS

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STA015

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Hardware Reset: 0x00

The registers are considered logically concatenated and contain the fractional values for the PLL, for

44.1KHz reference frequency.

(see also PLLFRAC_L and PLLFRAC_H registers)

ADPCM_SAMPLE_FREQ

Address: 0x53 (83)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

ADPCM_SF: Adpcm Sample Frequency

PCMDIVIDER

Address: 0x54 (84)

Type: RW

Software Reset: 0x01

Hardware Reset: 0x01

PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and

the SCKT (Serial Audio Transmitter Clock).

The relation is the following:

The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression:

1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation)

2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used)

3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used)

MSB

LSB

PF15

PF14

PF13

PF12

PF11

PF10

PF19

PF8

MSB

LSB

ADPCM_SF

0x02

8KHz

0x0A

16KHz

0x0E

32KHz

MSB

LSB

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

SCKT_freq

OCLK_freq

PCM_DIV

()

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