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MPC8572ECLPXATLD 数据表(PDF) 23 Page - Freescale Semiconductor, Inc |
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MPC8572ECLPXATLD 数据表(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 23 DDR2 and DDR3 SDRAM Controller 400 MHz tDDKHCS 1.95 — ns 3 MCS[n] output hold with respect to MCK tDDKHCX ns 3 800 MHz 0.917 — 667 MHz 1.10 — 533 MHz 1.48 — 400 MHz 1.95 — MCK to MDQS Skew tDDKHMH ns 4 800 MHz –0.375 0.375 <= 667 MHz –0.6 0.6 MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS ps 5 800 MHz 375 — 667 MHz 450 — 533 MHz 538 — 400 MHz 700 — MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX, tDDKLDX ps 5 800 MHz 375 — 667 MHz 450 — 533 MHz 538 — 400 MHz 700 — MDQS preamble start tDDKHMP ns 6 800 MHz –0.5 × tMCK – 0.375 –0.5 × tMCK +0.375 <= 667 MHz –0.5 × tMCK – 0.6 –0.5 × tMCK +0.6 MDQS epilogue end tDDKHME ns 6 800 MHz –0.375 0.375 Table 17. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3. Parameter Symbol 1 Min Max Unit Notes |
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