MPC8572ECLPXATLD datasheet(68/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

13.2

I2C AC Electrical Specifications

Table 54 provides the AC timing parameters for the I2C interfaces.

Table 54. I2C AC Electrical Specifications

At recommended operating conditions with OVDD of 3.3 V ± 5%. All values refer to VIH (min) and VIL (max) levels (see Table 2).

Parameter

Symbol1

Min

Max

Unit

SCL clock frequency

fI2C

0400

kHz4

Low period of the SCL clock

tI2CL

1.3

—

μs

High period of the SCL clock

tI2CH

0.6

—

μs

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

tI2SXKL

0.6

—

μs

Data setup time

tI2DVKH

100

—

Data input hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

μs

Data output delay time

tI2OVKL

—0.93

μs

Setup time for STOP condition

tI2PVKH

0.6

—

μs

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OVDD

—V

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH

0.2

× OVDD

—V

Capacitive load for each bus line

—

400

Notes:

1.The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the START condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the STOP condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time.

2. As a transmitter, the MPC8572E provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the

SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP

condition. When the MPC8572E acts as the I2C bus master while transmitting, the MPC8572E drives both SCL and SDA.

As long as the load on SCL and SDA are balanced, the MPC8572E would not cause unintended generation of START or

STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA

output delay time is required for the MPC8572E as transmitter, applicat ion note AN2919 referred to in note 4 below is

recommended.

3.The maximum tI2OVKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. The requirements for I2C frequency calculation must be followed. Refer to Freescale application note AN2919,

Determining

the I2C Frequency Divider Ratio for SCL.

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