MPC8572ECLPXATLD datasheet(54/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Local Bus Controller (eLBC)

Table 47 provides the DC electrical characteristics for the local bus interface operating at BVDD = 1.8 V

DC.

10.2

Local Bus AC Electrical Specifications

Table 48 describes the general timing parameters of the local bus interface at BVDD = 3.3 V DC.

Table 47. Local Bus DC Electrical Characteristics (1.8 V DC)

Parameter

Symbol

Min

Max

Unit

Supply voltage 1.8V

BVDD

1.71

1.89

High-level input voltage

VIH

0.65 x BVDD

BVDD + 0.3

Low-level input voltage

VIL

–0.3

0.35 x BVDD

Input current

(BVIN

1 = 0 V or BV

IN = BVDD)

IIN

TBD

μA

High-level output voltage

(IOH = –100 μA)

VOH

BVDD – 0.2

—

High-level output voltage

(IOH = –2 mA)

VOH

BVDD – 0.45

—

Low-level output voltage

(IOL = 100 μA)

VOL

—0.2

Low-level output voltage

(IOL = 2 mA)

VOL

—0.45

Note:

1. The symbol BVIN, in this case, represents the BVIN symbol referenced in Table 1.

Table 48. Local Bus General Timing Parameters (BVDD = 3.3 V DC)—PLL Enabled

At recommended operating conditions with BVDD of 3.3 V ± 5%.

Parameter

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

6.67

Local bus duty cycle

tLBKH/tLBK

—

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—

150

7,8

Input setup to local bus clock (except LGTA/LUPWAIT)

tLBIVKH1

1.8

—

3, 4

LGTA/LUPWAIT input setup to local bus clock

tLBIVKH2

1.7

—

3, 4

Input hold from local bus clock (except LGTA/LUPWAIT)

tLBIXKH1

1.0

—

3, 4

LGTA/LUPWAIT input hold from local bus clock

tLBIXKH2

1.0

—

3, 4

LALE output negation to high impedance for LAD/LDP

(LATCH hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except LAD/LDP and LALE)

tLBKHOV1

—2.3

—

Local bus clock to data valid for LAD/LDP

tLBKHOV2

—2.4

Local bus clock to address valid for LAD

tLBKHOV3

—2.3

Local bus clock to LALE assertion

tLBKHOV4

—2.3

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