MPC8572ECLPXATLD datasheet(45/140 Pages) FREESCALE

45 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 22. 4-Wire AC-Coupled SGMII Serial Link Connection Example

Change in VOS between “0” and “1”

VOS

——

—

Output current on short to GND

ISA, ISB

——

—

Note:

1. This will not align to DC-coupled SGMII. XVDD_SRDS2-Typ=1.1 V.

2. |VOD| = |VSD2_TXn - VSD2_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.

3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes

A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8572E’s SerDes 2 Control Register:

•The MSbit (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude - power up default);

•The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.

4. VOS is also referred to as output common mode voltage.

•

5.The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS2-Typ=1.1V, no common mode offset

variation (VOS =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and

SD2_TX[n].

Table 37. SGMII DC Transmitter Electrical Characteristics (continued)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

MPC8572E SGMII

SerDes Interface

Transmitter

SD2_TXn

SD_RXm

SD2_TXn

SD_RXm

Receiver

CTX

SD2_RXn

Receiver

Transmitter

SD_TXm

CTX

MPC8572ECLPXATLD 数据表(PDF) 45 Page - Freescale Semiconductor, Inc

MPC8572ECLPXATLD 数据表(HTML) 45 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载