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MPC8572ECLPXATLD 数据表(PDF) 14 Page - Freescale Semiconductor, Inc

部件名 MPC8572ECLPXATLD
功能描述  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
PDF  140 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8572ECLPXATLD 数据表(HTML) 14 Page - Freescale Semiconductor, Inc

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2
Power Sequencing
The MPC8572E requires its power rails to be applied in a specific sequence to ensure proper device
operation. These requirements are as follows for power up:
1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD_SRDS1 and SVDD_SRDS2, TVDD, XVDD_SRDS1 and
XVDD_SRDS2
2. GVDD
All supplies must be at their stable values within 50 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before
the voltage rails on the current step reach 10% of theirs.
To guarantee MCKE low during power-on reset, the above sequencing for GVDD is required. If there is no
concern about any of the DDR signals being in an indeterminate state during power-on reset, then the
sequencing for GVDD is not required.
Table 3. Output Drive Capability
Driver Type
Programmable
Output Impedance
(
Ω)
Supply
Voltage
Notes
Local bus interface utilities signals
25
35
BVDD = 3.3 V
BVDD = 2.5 V
1
45(default)
45(default)
125
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
DDR2 signal
18
36 (half strength mode)
GVDD = 1.8 V
2
DDR3 signal
20
40 (half strength mode)
GVDD = 1.5 V
2
eTSEC/10/100 signals
45
L/TVDD = 2.5/3.3 V
DUART, system control, JTAG
45
OVDD = 3.3 V
I2C
150
OVDD = 3.3 V
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105°C and at GVDD (min).



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