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L6460 数据表(PDF) 73 Page - STMicroelectronics |
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L6460 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 139 page  L6460 Power bridges Doc ID 17713 Rev 1 73/139 14.1.6 Synchronous buck regulator configuration (Bridge 3) Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as a single high current synchronous buck regulator using GPIOs pins in order to close the voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control loop using an internally generated PWM signal. The voltage will be set externally with a divider network and PWM duty cycle that can be programmed in order to ensure a proper regulation. The regulator will be enabled/disabled using serial interface and will implement a soft start strategy similar to that used by primary switching regulator. Table 27. Stepper fast decay MixDecPhX[4:0] Fast decay percentage during off time Unit Typ 00000 0 % 00001 6.25 % 00010 12.5 % 00011 18.75 % 00100 25 % 00101 31.25 % 00110 37.6 % 00111 43.75 % 01000 50 % 01001 56.25 % 01010 62.5 % 01011 68.75 % 01100 75 % 01101 81.25 % 01110 87.5 % 01111 93.75 % 1xxxx 100 % |
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