L6460 datasheet(29/139 Pages) STMICROELECTRONICS

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L6460

Electrical specifications

Doc ID 17713 Rev 1

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10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB).

11. This condition is intended to simulate an extra current on output.

12. This condition is intended to simulate a short circuit on output.

13. Rise and fall time are measured between 10% and 90% VSWmain output voltage.

14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSWDRV_FB).

15. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The

protection is performed by switching off the output bridge when current reaches values higher than the IOC max. No

protection could be guaranteed for values in the middle range between IMAX and IOC

16. In this cell X stands for 1 or 2, Y stands for A or B

17. In this cell X stands for 3 or 4, Y stands for A or B

18. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value

(MtrXSideYILimSel[1:0]= 11) is available.

19. Overcurrent Off time can be configured using SPI.

20. Rise and fall time are measured between 10% and 90% of DC output voltage. With device in full bridge configuration

(resistive load between outputs).

21. Default state for Aux1

22. Default state for Aux2

23. The regulated voltage can be calculated using the formula: VAUX_SW = VFBREF *(Ra+Rb)/Rb.

24. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2)

25. Rise and fall time is measured between 10% and 90% of output voltage.

26. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range.

27. The regulated voltage can be calculated using the formula: VAUX3_SW = VFBREF *(Ra+Rb)/Rb.

28. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VREF_FB).

29. The definition of LSB for this table is LSB=IMRmax/(27.5-1).

30. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the

“best straight line” approximating the ADC transfer curve.

31. The ADC ensures monotonic characteristic and no missing codes.

32. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1

LSB.

33. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB).

34. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 - 0.5 LSB), after

adjusting for offset error.

35. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is

reduced when the ADC is used in the 8- bit resolution mode.

36. Actual input capacitance depends on the pin that must be converted.

37. The definition of LSB for this table is LSB=IMRmax/(29-1).

38. All parameters are guaranteed in the range between VOL and VR Max.

39. Measured from DacValue[5:0] change in SPI interface.

40. VGPIO_SPI = 3.3 V unless otherwise specified

41. In this section reports the operational amplifier parameters that change when used as comparator.

42.

ΔVi is the differential voltage applied to input pins across the common voltage V

CM.

43. Measured between 50% of input and output signal.

44. Time measured from change in SPI interface to 50% of external pin transition.

45. Measured between nSS rising edge and 50% of Vout.

46. Specification applies to nSS, SCLK and MOSI pins.

47. Current is considered to be positive when flowing towards the IC

48. These times are measured at the pin output between specified VOH and VOL.

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