TMS320DM8167 datasheet(2/312 Pages) TI1

2 / 312 page

TMS320DM8168, TMS320DM8167

TMS320DM8166, TMS320DM8165

SPRS614 – MARCH 2011

www.ti.com

•

One 16/24-bit and One 16-bit Channel

– Flexible Asynchronous Protocol Control for

Interface to FPGA, CPLD, ASICs, etc.

•

Each Channel Splittable Into Dual 8-bit

Capture Channels

• Enhanced Direct-Memory-Access (EDMA)

Controller

– Two 165 MHz HD Video Display Channels

– Four Transfer Controllers

•

One 16/24/30-Bit and One 16-bit Channel

– 64/8 Independent DMA/QDMA Channels

– Simultaneous SD and HD Analog Output

• Seven 32-bit General-Purpose Timers

– Digital HDMI 1.3 transmitter with HDCP up to

165-MHz pixel clock

• One System Watchdog Timer

– Advanced Video Processing Features Such

• Three Configurable UART/IrDA/CIR Modules

as Scan/Format/Rate Conversion

– UART0 With Modem Control Signals

– Three Graphics Layers and Compositors

– Supports up to 3.6864 Mbps UART

• Dual 32-bit DDR2/3 SDRAM Interfaces

– SIR, MIR, FIR (4.0 MBAUD), and CIR

– Supports up to DDR2-800 and DDR3-1600

• One 40-MHz Serial Peripheral Interface (SPI)

– Up to Eight x8 Devices Total

With Four Chip-Selects

– 2 GB Total Address Space

• SD/SDIO serial interface (1-/4-Bit)

– Dynamic Memory Manager (DMM)

• Dual Inter-Integrated Circuit ( I2C BUS®) Ports

•

Programmable Multi-Zone Memory

• Three Multichannel Audio Serial Ports

Mapping and Interleaving

– One Six-Serializer Transmit/Receive Port

•

Enables Efficient 2D Block Accesses

– Two Dual-Serializer Transmit/Receive Ports

•

Supports Tiled Objects in 0°, 90°, 180°, or

– DIT-Capable For S/PDIF (All Ports)

270 Orientation and Mirroring

• Multichannel Buffered Serial Port (McBSP)

•

Optimizes Interlaced Accesses

– Transmit/Receive Clocks up to 48 MHz

• One PCI Express® (PCIe®) 2.0 Port With

– Two Clock Zones and Two Serial Data Pins

Integrated PHY

– Supports TDM, I2S, and Similar Formats

– Single Port With 1 or 2 Lanes at 5.0 GT/s

• Real-Time Clock (RTC)

– Configurable as Root Complex or Endpoint

– One-Time or Periodic Interrupt Generation

• Serial ATA (SATA) 3.0 Gbps Controller With

• Up to 64 General-Purpose I/O (GPIO) Pins

Integrated PHYs

• On-Chip ARM® ROM Bootloader (RBL)

– Direct Interface for Two Hard Disk Drives

• Power, Reset, and Clock Management

– Hardware-Assisted Native Command

– SmartReflex™ Technology (Level 2)

Queuing (NCQ) from up to 32 Entries

– Seven Independent Core Power Domains

– Supports Port Multiplier and

– Clock Enable/Disable Control For

Command-Based Switching

Subsystems and Peripherals

• Two 10/100/1000 Mbps Ethernet MACs (EMAC)

• IEEE-1149.1 (JTAG) and IEEE-1149.7 (cJTAG)

– IEEE 802.3 Compliant (3.3V I/O Only)

Compatible

– MII and GMII Media Independent I/Fs

• 1031-Pin Pb-Free BGA Package (CYG Suffix),

– Management Data I/O (MDIO) Module

0.65-mm Ball Pitch

• Dual USB 2.0 Ports With Integrated PHYs

• Via Channel™ Technology Enables use of

– USB 2.0 High-/Full-Speed Client

0.8-mm Design Rules

– USB 2.0 High-/Full-/Low-Speed Host

• 40-nm CMOS Technology

– Supports End Points 0-15

• 3.3-V Single-Ended LVCMOS I/Os (except for

• General Purpose Memory Controller (GPMC)

DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN

– 8-/16-bit Multiplexed Address/Data Bus

at 1.8 V)

– Up to 6 Chip Selects With up to 256M-Byte

• Applications

Address Space per Chip Select Pin

– Video Encode/Decode/Transcode/Transrate

– Glueless Interface to NOR Flash, NAND

– Video Security

Flash (With BCH and Hamming Error Code

– Video Conferencing

Detection), SRAM and Pseudo-SRAM

– Video Infrastructure

– Error Locator Module (ELM) Outside of

– Media Server

GPMC to Provide Up to 16-Bit/512-Bytes

– Digital Signage

Hardware ECC for NAND

Device Summary

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Product Folder Link(s): TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165

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