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TMS320DM8167 数据表(PDF) 53 Page - Texas Instruments |
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TMS320DM8167 数据表(HTML) 53 Page - Texas Instruments |
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53 / 312 page  TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 www.ti.com SPRS614 – MARCH 2011 3.2.2 DDR2/3 Memory Controller Signals Table 3-2. DDR2/3 Memory Controller 0 Terminal Functions SIGNAL TYPE(1) OTHER(2) DESCRIPTION NAME NO. DDR[0]_CLK[0] B12 O DVDD_DDR[0] DDR[0] Clock 0 DDR[0]_CLK[0] A12 O DVDD_DDR[0] DDR[0] Negative Clock 0 DDR[0]_CLK[1] A15 O DVDD_DDR[0] DDR[0] Clock 1 DDR[0]_CLK[1] B15 O DVDD_DDR[0] DDR[0] Negative Clock 1 DDR[0]_CKE C18 O DVDD_DDR[0] DDR[0] Clock Enable DDR[0]_WE E13 O DVDD_DDR[0] DDR[0] Write Enable DDR[0]_CS[0] B17 O DVDD_DDR[0] DDR[0] Chip Select 0 DDR[0]_CS[1] F18 O DVDD_DDR[0] DDR[0] Chip Select 1 DDR[0]_RAS D13 O DVDD_DDR[0] DDR[0] Row Address Strobe output DDR[0]_CAS C13 O DVDD_DDR[0] DDR[0] Column Address Strobe output DDR[0]_DQM[3] D9 O DVDD_DDR[0] DDR[0] Data Mask outputs DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQM[2] G9 O DVDD_DDR[0] DDR[0]_DQM[2]: For DDR[0]_D[23:16] DDR[0]_DQM[1] B5 O DVDD_DDR[0] DDR[0]_DQM[1]: For DDR[0]_D[15:8] DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0] DDR[0]_DQM[0] C2 O DVDD_DDR[0] DDR[0]_DQS[3] B9 I/O DVDD_DDR[0] Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. DDR[0]_DQS[2] B8 I/O DVDD_DDR[0] They are used to synchronize the data transfers. DDR[0]_DQS[1] B4 I/O DVDD_DDR[0] DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0] F4 I/O DVDD_DDR[0] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0] DDR[0]_DQS[3] A9 I/O DVDD_DDR[0] Complimentary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs DDR[0]_DQS[2] A8 I/O DVDD_DDR[0] when reading. They are used to synchronize the data transfers. DDR[0]_DQS[1] A4 I/O DVDD_DDR[0] DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0] E3 I/O DVDD_DDR[0] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0] DDR[0]_ODT[0] E18 O DVDD_DDR[0] DDR[0] On-Die Termination for Chip Select 0. DDR[0]_ODT[1] A16 O DVDD_DDR[0] DDR[0] On-Die Termination for Chip Select 1. DDR[0]_RST D18 O DVDD_DDR[0] DDR[0] Reset output DDR[0]_BA[2] N15 O DVDD_DDR[0] DDR[0]_BA[1] B14 O DVDD_DDR[0] DDR[0] Bank Address outputs DDR[0]_BA[0] F13 O DVDD_DDR[0] (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. Copyright © 2011, Texas Instruments Incorporated Device Pins 53 Submit Documentation Feedback Product Folder Link(s): TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 |
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