TMS320DM8167 datasheet(35/312 Pages) TI1

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TMS320DM8168, TMS320DM8167

TMS320DM8166, TMS320DM8165

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SPRS614 – MARCH 2011

2.10.5 C674x Memory Map

Because the C674x DSP has specific hardwired address decoding built in, the C674x memory map is

slightly different than that of the Cortex™-A8. The C674x has a separate CFG bus which is used to

access L4 peripherals and its UMAP1 bus has a direct connection into HDVICP2 SL2 (HDVICP2-0 and

HDVICP2-1 only) memories. All C674x MDMA port accesses are routed through the DEMMU for address

translation.

Table 2-30. C674x Memory Map

START ADDRESS

REGION NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

(HEX)

Reserved(1)

0x0000 0000

0x003F FFFF

4MB

Reserved

UMAP1(1)

0x0040 0000

0x0043 FFFF

256KB

C674x UMAP1 (HDVICP2-0 SL2)

Reserved (UMAP1)(1)

0x0044 0000

0x004F FFFF

768KB

Reserved

UMAP1(1)

0x0050 0000

0x0053 FFFF

256KB

C674x UMAP1 (HDVICP2-1 SL2)

Reserved (UMAP1)(1)

0x0054 0000

0x005F FFFF

768KB

Reserved

Reserved(1)

0x0060 0000

0x007F FFFF

2MB

Reserved

L2 SRAM(1)

0x0080 0000

0x0083 FFFF

256KB

C674x UMAP0 (L2 RAM)

Reserved(1)

0x0084 0000

0x00DF FFFF

5888KB

Reserved

L1P SRAM(1)

0x00E0 0000

0x00E0 7FFF

32KB

C674x L1P Cache/RAM

Reserved(1)

0x00E0 8000

0x00EF FFFF

992KB

Reserved

L1D SRAM(1)

0x00F0 0000

0x00F0 7FFF

32KB

C674x L1D Cache/RAM

Reserved(1)

0x00F0 8000

0x017F FFFF

9184KB

Reserved

Internal CFG(2)(3)

0x0180 0000

0x01BF FFFF

4MB

C674x Internal CFG registers

Reserved(3)

0x01C0 0000

0x07FF FFFF

100MB

Reserved

L4 Standard Domain(3)

0x0800 0000

0x08FF FFFF

16MB

Peripheral Domain (see Table 2-26)

EDMA TPCC(3)

0x0900 0000

0x090F FFFF

1MB

EDMA TPCC Registers

Reserved(3)

0x0910 0000

0x097F FFFF

7MB

Reserved

EDMA TPTC0(3)

0x0980 0000

0x098F FFFF

1MB

EDMA TPTC0 Registers

EDMA TPTC1(3)

0x0990 0000

0x099F FFFF

1MB

EDMA TPTC1 Registers

EDMA TPTC2(3)

0x09A0 0000

0x09AF FFFF

1MB

EDMA TPTC2 Registers

EDMA TPTC3(3)

0x09B0 0000

0x09BF FFFF

1MB

EDMA TPTC3 Registers

Reserved(3)

0x09C0 0000

0x09FF FFFF

4MB

Reserved

L4 High-Speed

0x0A00 0000

0x0AFF FFFF

16MB

Peripheral Domain (see Table 2-27)

Domain(3)

Reserved(3)

0x0B00 0000

0x0FFF FFFF

80MB

Reserved

C674x L1/L2(4)

0x1000 0000

0x10FF FFFF

16MB

C674x Internal Global Address

MDMA L3(5)

0x1100 0000

0xFFFF FFFF

3824MB

DEMMU Mapped L3 Regions

(1)

Addresses 0x0000 0000 to 0x017F FFFF are internal to the C674x device.

(2)

Addresses 0x0180 0000 to 0x01BF FFFF are reserved for C674x internal CFG registers.

(3)

Addresses 0x01C0 0000 to 0x0FFF FFFF are mapped to the C674x CFG bus.

(4)

Addresses 0x1000 0000 to 0x10FF FFFF are mapped to C674x internal addresses 0x0000 0000 to 0x00FF FFFF.

(5)

These accesses are routed through the DEMMU where the page tables translate to the physical L3 addresses shown in Table 2-25.

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