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TMS320DM8167 数据表(PDF) 79 Page - Texas Instruments |
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TMS320DM8167 数据表(HTML) 79 Page - Texas Instruments |
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79 / 312 page ![]() TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 www.ti.com SPRS614 – MARCH 2011 3.2.11 Peripheral Component Interconnect Express (PCIe) Signals Table 3-14. PCIe Terminal Functions SIGNAL TYPE(1) OTHER(2) DESCRIPTION NAME NO. PCIE_TXP0 AB31 O PCIE Transmit Data Lane 0. VDDR_PCIE When the PCIe SERDES are powered down, or if this lane is not used, PCIE_TXN0 AB30 O these pins should be left unconnected. PCIE_RXP0 Y29 I PCIE Receive Data Lane 0. VDDR_PCIE When the PCIe SERDES are powered down, or if this lane is not used, PCIE_RXN0 V29 I these pins should be left unconnected. PCIE_TXP1 Y27 O PCIE Transmit Data Lane 1. VDDR_PCIE When the PCIe SERDES are powered down, or if this lane is not used, PCIE_TXN1 AB28 O these pins should be left unconnected. PCIE_RXP1 V31 I PCIE Receive Data Lane 1. VDDR_PCIE When the PCIe SERDES are powered down, or if this lane is not used, PCIE_RXN1 V30 I these pins should be left unconnected. SERDES_CLKP AB34 I VDD_LJCB PCIE Serdes Reference Clock Inputs. Shared between PCI Express and Serial ATA. When neither PCI Express nor Serial ATA are used, these SERDES_CLKN AB33 I VDD_LJCB pins should be left unconnected. (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. Copyright © 2011, Texas Instruments Incorporated Device Pins 79 Submit Documentation Feedback Product Folder Link(s): TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 |
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