TMS320DM8167 datasheet(33/312 Pages) TI1

33 / 312 page

TMS320DM8168, TMS320DM8167

TMS320DM8166, TMS320DM8165

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SPRS614 – MARCH 2011

2.10.4 Cortex™-A8 Memory Map

The Cortex™-A8 includes an memory management unit (MMU) to translate virtual addresses to physical

addresses which are then decoded within the Host ARM Subsystem. The subsystem includes its own

ROM and RAM, as well as configuration registers for its interrupt controller and secure state machine.

These addresses are hard-coded within the subsystem. In addition, the upper 2GB of address space is

routed to a special port (Master 0) intended for low-latency access to DDR memory. All other physical

addresses are routed to the L3 port (Master 1) where they are decoded by the device infrastructure. The

Cortex™-A8 memory map is shown in Table 2-29.

Table 2-29. Cortex™-A8 Memory Map

START ADDRESS

REGION NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

(HEX)

Boot Space

0x0000 0000

0x000F FFFF

1MB

Boot Space

L3 Target Space

0x0000 0000

0x1FFF FFFF

512MB

GPMC

0x2000 0000

0x2FFF FFFF

256MB

PCIe Gen2 Targets

0x3000 0000

0x3FFF FFFF

256MB

Reserved

ROM internal(1)

0x4000 0000

0x4001 FFFF

128KB

Reserved

0x4002 0000

0x4002 BFFF

48KB

Public

0x4002 C000

0x400F FFFF

848KB

Reserved

Reserved(1)

0x4010 0000

0x401F FFFF

1MB

Reserved

Reserved(1)

0x4020 0000

0x402E FFFF

960KB

Reserved

0x402F 0000

0x402F FFFF

64KB

Reserved

L3 Target Space

0x4030 0000

0x4033 FFFF

256KB

OCMC SRAM

0x4034 0000

0x403F FFFF

768KB

Reserved

0x4040 0000

0x4043 FFFF

256KB

OCMC SRAM

0x4044 0000

0x404F FFFF

768KB

Reserved

0x4050 0000

0x407F FFFF

3MB

Reserved

0x4080 0000

0x4083 FFFF

256KB

C674x UMAP0 (L2 RAM)

0x4084 0000

0x40DF FFFF

5888KB

Reserved

0x40E0 0000

0x40E0 7FFF

32KB

C674x L1P Cache/RAM

0x40E0 8000

0x40EF FFFF

992KB

Reserved

0x40F0 0000

0x40F0 7FFF

32KB

C674x L1D Cache/RAM

0x40F0 8000

0x40FF FFFF

992KB

Reserved

0x4100 0000

0x41FF FFFF

16MB

Reserved

0x4200 0000

0x43FF FFFF

32MB

Reserved

0x4400 0000

0x44BF FFFF

12MB

L3 configuration registers

0x44C0 0000

0x45FF FFFF

20MB

Reserved

0x4600 0000

0x463F FFFF

4MB

McASP0

0x4640 0000

0x467F FFFF

4MB

McASP1

0x4680 0000

0x46BF FFFF

4MB

McASP2

0x46C0 0000

0x46FF FFFF

4MB

HDMI 1.3 Tx

0x4700 0000

0x473F FFFF

4MB

McBSP

0x4740 0000

0x477F FFFF

4MB

USB2.0 Registers / CPPI

0x4780 0000

0x47BF FFFF

4MB

Reserved

0x47C0 0000

0x47FF FFFF

4MB

Reserved

0x4800 0000

0x481F FFFF

2MB

Standard Peripheral domain (see Table 2-26)

ARM Subsystem

0x4820 0000

0x4820 0FFF

4KB

Cortex™-A8 Interrupt Controller

INTC(1)

Reserved(1)

0x4820 1000

0x4823 FFFF

252KB

Reserved

(1)

These addresses are decoded within the Cortex™-A8 subsystem.

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