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TMS320DM8167 数据表(PDF) 1 Page - Texas Instruments |
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TMS320DM8167 数据表(HTML) 1 Page - Texas Instruments |
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1 / 312 page  TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 www.ti.com SPRS614 – MARCH 2011 TMS320DM816x DaVinci Digital Media Processors Check for Samples: TMS320DM8168, TMS320DM8167, TMS320DM8166, TMS320DM8165 1 Device Summary 1.1 Features 1234567891011 Multiply Supported up to: • High-Performance DaVinci™ Digital Media Processors – 2 SP x SP → SP Per Clock – ARM® Cortex™-A8 RISC MPU – 2 SP x SP → DP Every Two Clocks • Up to 1.2 GHz – 2 SP x DP → DP Every Three Clocks – C674x VLIW DSP – 2 DP x DP → DP Every Four Clocks • Up to 1.0 GHz • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-bit Multiplies • Up to 8000/6000 C674x MIPS/MFLOPS including Complex Multiplies, or Eight 8 x • Fully Software-Compatible with C67x+™ 8-Bit Multiplies per Clock Cycle and C64x+™ • C674x Two-Level Memory Architecture • ARM® Cortex™-A8 Core – 32K-Byte L1P and L1D RAM/Cache – ARMv7 Architecture – 256K-Byte L2 Unified Mapped RAM/Caches • In-Order, Dual-Issue, Superscalar • DSP/EDMA Memory Management Unit Microprocessor Core (DEMMU) • NEON™ Multimedia Architecture – Maps C674x DSP and EMDA TCB Memory – Supports Integer and Floating Point Accesses to System Addresses (VFPv3-IEEE754 compliant) • 512K-Bytes On-Chip Memory Controller • Jazelle® RCT Execution Environment (OCMC) RAM • ARM® Cortex™-A8 Memory Architecture • Up to Three Programmable High-Definition – 32K-Byte Instruction and Data Caches Video Image Coprocessing (HDVICP2) Engines – 256K-Byte L2 Cache – Encode, Decode, Transcode Operations – 64K-Byte RAM, 48K-Byte Boot ROM – H.264, MPEG2, VC1, MPEG4 SP/ASP • TMS320C674x Floating-Point VLIW DSP • SGX530 3D Graphics Engine (available only on – 64 General-Purpose Registers (32-Bit) the DM8168/DM8166 device) – Six ALU (32-/40-Bit) Functional Units – Delivers up to 30 MTriangles/s • Supports 32-Bit Integer, SP (IEEE Single – Universal Scalable Shader Engine Precision/32-Bit) and DP (IEEE Double – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, Precision/64-Bit) Floating Point OpenVG™ 1.0, OpenMax™ API Support • Supports up to Four SP Adds Per Clock – Advanced Geometry DMA Driven Operation and Four DP Adds Every Two Clocks – Programmable HQ Image Anti-Aliasing • Supports up to Two Floating-Point (SP or • Endianness DP) Approximate Reciprocal or Square – ARM/DSP Instructions/Data – Little Endian Root Operations Per Cycle • HD Video Processing Subsystem (HDVPSS) – Two Multiply Functional Units – Two 165 MHz HD Video Capture Channels • Mixed-Precision IEEE Floating-Point 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 DaVinci, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments. 3 Cortex, NEON are trademarks of ARM Ltd or its subsidiaries. 4 ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries. 5 USSE, POWERVR are trademarks of Imagination Technologies Limited. 6 OpenVG, OpenMax are trademarks of Khronos Group Inc. 7 Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries. 8 I2C BUS is a registered trademark of NXP B.V. Corporation Netherlands. 9 PCI Express, PCIe are registered trademarks of PCI-SIG. 10 OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries. 11 All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative Copyright © 2011, Texas Instruments Incorporated or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
类似零件编号 - TMS320DM8167 |
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类似说明 - TMS320DM8167 |
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