TMS320DM8167 datasheet(9/312 Pages) TI1

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ARM Cortex™-A8

NEON

ETM

256KB L2$

32KB L1I$ 32KB L1D$

Arbiter

128

ICECrusher

48KB ROM

64KB RAM

ARM Cortex-A8

Interrupt Controller

(AINTC)

DMM

128

SYSCLK2

128

System Events

DEVOSC

Trace

Debug

TMS320DM8168, TMS320DM8167

TMS320DM8166, TMS320DM8165

www.ti.com

SPRS614 – MARCH 2011

Figure 2-1. ARM Cortex-A8 Subsystem Block Diagram

2.3.1

ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor

is a member of ARM Cortex family of general-purpose microprocessors. This processor is targeted at

multi-tasking applications where full memory management, high performance, low die size, and low power

are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic

to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture

and provides a complete high-performance subsystem, including:

•

ARM Cortex-A8 integer core

•

Superscalar ARMv7 instruction set

•

Thumb-2 instruction set

•

Jazelle RCT acceleration

•

CP14 debug coprocessor

•

CP15 system control coprocessor

•

NEON 64-/128-bit hybrid SIMD engine for multimedia

•

Enhanced memory management unit (MMU)

•

Separate level-1 instruction and data caches

•

Integrated level-2 cache

•

128-bit interconnect to system memories and peripherals

•

Embedded trace module (ETM).

2.3.2

Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an

embedded trace module (ETM). The ETM consists of two parts:

•

The Trace port provides real-time trace capability for the ARM Cortex-A8.

•

Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB

has a 32KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace

data.

For more details on the ETB, see Section 8.4.2.

Device Overview

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