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TMS320DM8167 数据表(PDF) 11 Page - Texas Instruments |
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TMS320DM8167 数据表(HTML) 11 Page - Texas Instruments |
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11 / 312 page  Instruction Fetch C674x+ CPU Register File A Register File B Cache Control Memory Protect Bandwidth Mgmt L1P 256 Cache Control Memory Protect Bandwidth Mgmt L1D 64 64 8 x 32 32K Bytes L1D RAM/ Cache 32K Bytes L1P RAM/ Cache w/EDC 256 Cache Control Memory Protect Bandwidth Mgmt L2 256K Bytes L2 RAM w/ECC 256 HDVICP2 Host SL2 Port 256 CFG MDMA SDMA EMC Power Down Interrupt Controller IDMA 256 256 256 256 256 128 High- Performance Switch Fabric 128 Peripherals 32 TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 www.ti.com SPRS614 – MARCH 2011 2.4 DSP Subsystem The DSP Subsystem includes the following features: • C674x DSP CPU • 32KB L1 Program (L1P)/Cache (up to 32KB) with Error Detection Code (EDC) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 256KB L2 Unified Mapped RAM/Cache with Error Correction Code (ECC) • Direct Connection to the HDVICP2 Host SL2 Port for HDVICP2-0/1 • Little endian Figure 2-2. C674x Megamodule Block Diagram Copyright © 2011, Texas Instruments Incorporated Device Overview 11 Submit Documentation Feedback Product Folder Link(s): TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 |
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