AFS090 datasheet(128/334 Pages) MICROSEMI

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Device Architecture

2- 11 2

R e v isio n 2

(conversion that starts

before a previously started conversion is finished). The total time for

calibration still remains 3,840 ADCCLK cycles.

ADC Example

This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode

for a system that runs at 66 MHz. Assume the acquisition times defined in Table 2-44 on page 2-110 for

10-bit mode, which gives 0.549 µs as a minimum hold time.

The period of SYSCLK: tSYSCLK = 1/66 MHz = 0.015 µs

Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK

requirement. A higher TVC leads to a higher ADCCLK period.

The minimum TVC is chosen so that tdistrib and tpost-cal can be run faster. The period of ADCCLK with a

TVC of 1 can be computed by EQ 24.

EQ 24

The STC value can now be computed by using the minimum sample/hold time from Table 2-44 on

page 2-110, as shown in EQ 25.

EQ 25

You must round up to 3 to accommodate the minimum sample time requirement. The actual sample time,

tsample, with an STC of 3, is now equal to 0.6 µs, as shown in EQ 26

EQ 26

Microsemi recommends post-calibration for temperature drift over time, so post-calibration is enabled.

The post-calibration time, tpost-cal, can be computed by EQ 27. The post-calibration time is 0.24 µs.

EQ 27

The distribution time, tdistrib, is equal to 1.2 µs and can be computed as shown in EQ 28 (N is number of

bits, referring back to EQ 8 on page 2-96).

EQ 28

The total conversion time can now be summated, as shown in EQ 29 (referring to EQ 23 on page 2-111).

tsync_read + tsample + tdistrib + tpost-cal + tsync_write = (0.015 + 0.60 + 1.2 + 0.24 + 0.015) µs = 2.07 µs

EQ 29

The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is shown in

Table 2-47:

Table 2-47 • Optimal Setting at 66 MHz in 10-Bit Mode

TVC[7:0]

= 1

= 0x01

STC[7:0]

= 3

= 0x03

MODE[3:0]

= b'0100

= 0x4*

Note:

No power-down after every conversion is chosen in this case; however, if the application is

power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any

performance.

tADCCLK

41 TVC

()

tSYSCLK

41 1

()

0.015 µs

0.12 µs

STC

tsample

tADCCLK

--------------------

–

0.549 µs

0.12 µs

-----------------------

–

4.575 2

–

2.575

tsample

2STC

() t

ADCCLK

() t

ADCCLK

5 0.12 µs

0.6 µs

tpost-cal

2tADCCLK

0.24 µs

tdistrib

NtADCCLK

10 0.12

1.2 µs

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