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AFS090 数据表(PDF) 135 Page - Microsemi Corporation |
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AFS090 数据表(HTML) 135 Page - Microsemi Corporation |
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135 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 119 Analog System Characteristics Table 2-49 • Analog Channel Specifications Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise), Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Condition Min. Typ. Max. Units Voltage Monitor Using Analog Pads AV, AC and AT (using prescaler) Input Voltage (Prescaler) Refer to Table 3-2 on page 3-3 VINAP Uncalibrated Gain and Offset Errors Refer to Table 2-51 on page 2-124 Calibrated Gain and Offset Errors Refer to Table 2-52 on page 2-125 Bandwidth1 100 KHz Input Resistance Refer to Table 3-3 on page 3-4 Scaling Factor Prescaler modes (Table 2-57 on page 2-132) Sample Time 10 µs Current Monitor Using Analog Pads AV and AC VRSM1 Maximum Differential Input Voltage VAREF / 10 mV Resolution Refer to "Current Monitor" section Common Mode Range – 10.5 to +12 V CMRR Common Mode Rejection Ratio DC – 1 KHz 60 dB 1 KHz - 10 KHz 50 dB > 10 KHz 30 dB tCMSHI Strobe High time ADC conv. time 200 µs tCMSHI Strobe Low time 5 µs tCMSHI Settling time 0.02 µs Accuracy Input differential voltage > 50 mV –2 –(0.05 x VRSM) to +2 + (0.05 x VRSM) mV Notes: 1. VRSM is the maximum voltage drop across the current sense resistor. 2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits. 3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency. 4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance allowed across the AT pins is 500 pF. 5. The temperature offset is a fixed positive value. 6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad. 7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User’s Guide. |
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