AFS090 datasheet(137/334 Pages) MICROSEMI

137 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 121

Digital Input using Analog Pads AV, AC and AT

VIND2,3

Input Voltage

Refer to Table 3-2 on page 3-3

VHYSDIN

Hysteresis

0.3

VIHDIN

Input High

1.2

VILDIN

Input Low

0.9

VMPWDIN

Minimum Pulse With

FDIN

Maximum Frequency

MHz

ISTBDIN

Input Leakage Current

µA

IDYNDIN

Dynamic Current

µA

tINDIN

Input Delay

Gate Driver Output Using Analog Pad AG

Voltage Range

Refer to Table 3-2 on page 3-3

Output Current Drive

High Current Mode6 at 1.0 V

±20

Low Current Mode: ±1 µA

0.8

1.0

1.3

µA

Low Current Mode: ±3 µA

2.0

2.7

3.3

µA

Low Current Mode: ± 10 µA

7.4

9.0

11.5

µA

Low Current Mode: ± 30 µA

21.0

27.0

32.0

µA

IOFFG

Maximum Off Current

100

Maximum switching rate High Current Mode6 at 1.0 V, 1

Ω resistive load

1.3

MHz

Low Current Mode:

±1 µA, 3 M

Ω resistive load

3KHz

Low Current Mode:

±3 µA, 1 M

Ω resistive load

7KHz

Low Current Mode:

±10 µA, 300 k

Ω resistive load

KHz

Low Current Mode:

±30 µA, 105 k

Ω resistive load

KHz

Table 2-49 • Analog Channel Specifications (continued)

Commercial Temperature Range Conditions, TJ = 85°C (unless noted otherwise),

Typical: VCC33A = 3.3 V, VCC = 1.5 V

Parameter

Description

Condition

Min.

Typ.

Max.

Units

Notes:

1. VRSM is the maximum voltage drop across the current sense resistor.

2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no

reliability concern on digital inputs as long as VIND does not exceed these limits.

3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.

4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance

allowed across the AT pins is 500 pF.

5. The temperature offset is a fixed positive value.

6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on

voltage on the pad.

7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer

to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the

Fusion FPGA Fabric User’s

Guide.

AFS090 数据表(PDF) 137 Page - Microsemi Corporation

AFS090 数据表(HTML) 137 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AFS090 数据表(PDF) 137 Page - Microsemi Corporation

AFS090 数据表(HTML) 137 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载