| 数据搜索系统,热门电子元器件搜索 |
|
AFS090 数据表(PDF) 144 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
AFS090 数据表(HTML) 144 Page - Microsemi Corporation |
|
144 / 334 page ![]() Device Architecture 2- 12 8 R e v isio n 2 Analog Configuration MUX The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter. Microsemi Libero IDE will generate IP that will load and configure the Analog Block via the ACM. However, users are not limited to using the Libero IDE IP. This section provides a detailed description of the ACM's register map, truth tables for proper configuration of the Analog Block and RTC, as well as timing waveforms so users can access and control the ACM directly from their designs. The Analog Block contains four 8-bit latches per Analog Quad that are initialized through the ACM. These latches act as configuration bits for Analog Quads. The ACM block runs from the core voltage supply (1.5 V). Access to the ACM is achieved via 8-bit address and data busses with enables. The pin list is provided in Table 2-36 on page 2-80. The ACM clock speed is limited to a maximum of 10 MHz, more than sufficient to handle the low-bandwidth requirements of configuring the Analog Block and the RTC (sub-block of the Analog Block). Table 2-54 decodes the ACM address space and maps it to the corresponding Analog Quad and configuration byte for that quad. Table 2-54 • ACM Address Decode Table for Analog Quad ACMADDR [7:0] in Decimal Name Description Associated Peripheral 0 – – Analog Quad 1 AQ0 Byte 0 Analog Quad 2 AQ0 Byte 1 Analog Quad 3 AQ0 Byte 2 Analog Quad 4 AQ0 Byte 3 Analog Quad 5 AQ1 Byte 0 Analog Quad . . . . . . . . . Analog Quad 36 AQ8 Byte 3 Analog Quad 37 AQ9 Byte 0 Analog Quad 38 AQ9 Byte 1 Analog Quad 39 AQ9 Byte 2 Analog Quad 40 AQ9 Byte 3 Analog Quad 41 Undefined Analog Quad . . . . . . Undefined Analog Quad 63 Undefined RTC 64 COUNTER0 Counter bits 7:0 RTC 65 COUNTER1 Counter bits 15:8 RTC 66 COUNTER2 Counter bits 23:16 RTC 67 COUNTER3 Counter bits 31:24 RTC 68 COUNTER4 Counter bits 39:32 RTC 72 MATCHREG0 Match register bits 7:0 RTC |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |