AFS090 datasheet(151/334 Pages) MICROSEMI

151 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 135

Figure 2-97 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)

Table 2-67 • I/O Standards Supported by Bank Type

I/O Bank

Single-Ended I/O Standards

Differential I/O

Standards

Voltage-Referenced

Hot-

Swap

Standard I/O

LVTTL/LVCMOS 3.3 V, LVCMOS

2.5 V / 1.8 V / 1.5 V, LVCMOS

2.5/5.0 V

––

Yes

Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS

2.5 V / 1.8 V / 1.5 V, LVCMOS

2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-

LVPECL

and

LVDS

––

Pro I/O

LVTTL/LVCMOS 3.3 V, LVCMOS

2.5 V / 1.8 V / 1.5 V, LVCMOS

2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-

LVPECL

and

LVDS

GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V,

HSTL Class I and II, SSTL2 Class I

and II, SSTL3 Class I and II

Yes

Bank 1

Bank 0

I/O Pad

If needed, the VREF for a given

minibank can be provided by

any I/O within the minibank.

CCC

Up to five VREF

minibanks within

an I/O bank

VREF signal scope is

between 8 and 18 I/Os.

Common VREF

signal for all I/Os

in VREF minibanks

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