AFS090 datasheet(156/334 Pages) MICROSEMI

156 / 334 page

Device Architecture

2- 14 0

R e v isio n 2

I/O Registers

Each I/O module contains several input, output, and enable registers. Refer to Figure 2-98 for a

simplified representation of the I/O block.

The number of input registers is selected by a set of switches (not shown in Figure 2-98) between

registers to implement single or differential data transmission to and from the FPGA core. The Designer

software sets these switches for the user.

A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input

Note:

Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on

page 2-141 for more information).

Figure 2-98 • I/O Block Logical Representation

Input

Reg

E = Enable Pin

PAD

OCE

ICE

Input

Reg

Input

Reg

CLR/PRE

Pull-Up/Down

Resistor Control

Signal Drive Strength

and Slew-Rate Control

Output

Reg

Output

Reg

To FPGA Core

From FPGA Core

Output

Enable

Reg

OCE

I/O / CLR or I/O / PRE / OCE

I/O / Q0

I/O / Q1

I/O / ICLK

I/O / D0

I/O / D1 / ICE

I/O / OCLK

I/O / OE

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