MPC5643L datasheet(17/136 Pages) FREESCALE

17 / 136 page

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 8.1

Freescale Semiconductor

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Master or slave operation

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Programmable master bit rates

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Programmable clock polarity and phase

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End-of-transmission interrupt flag

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Programmable transfer baud rate

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Programmable data frames from 4 to 16 bits

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As many as 8 chip select lines available, depending on package and pin multiplexing

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4 clock and transfer attributes registers

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Chip select strobe available as alternate function on one of the chip select pins for de-glitching

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FIFOs for buffering as many as 5 transfers on the transmit and receive side

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Queueing operation possible through use of the eDMA

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General purpose I/O functionality on pins when not used for SPI

1.5.30

FlexPWM

The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single

half-bridge power stage. Two modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is

present. Additionally, four fault input channels are provided per FlexPWM module.

This PWM is capable of controlling most motor types, including:

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AC induction motors (ACIM)

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Permanent Magnet AC motors (PMAC)

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Brushless (BLDC) and brush DC motors (BDC)

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Switched (SRM) and variable reluctance motors (VRM)

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Stepper motors

A FlexPWM module implements the following features:

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16 bits of resolution for center, edge aligned, and asymmetrical PWMs

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Maximum operating frequency as high as 120 MHz

— Clock source not modulated and independent from system clock (generated via secondary FMPLL)

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Fine granularity control for enhanced resolution of the PWM period

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PWM outputs can operate as complementary pairs or independent channels

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Ability to accept signed numbers for PWM generation

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Independent control of both edges of each PWM output

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Synchronization to external hardware or other PWM supported

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Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

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Multiple ADC trigger events can be generated per PWM cycle via hardware

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Fault inputs can be assigned to control multiple PWM outputs

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Programmable filters for fault inputs

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Independently programmable PWM output polarity

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Independent top and bottom deadtime insertion

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Each complementary pair can operate with its own PWM frequency and deadtime values

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Individual software control for each PWM output

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All outputs can be forced to a value simultaneously

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PWMX pin can optionally output a third signal from each channel

MPC5643L 数据表(PDF) 17 Page - Freescale Semiconductor, Inc

MPC5643L 数据表(HTML) 17 Page - Freescale Semiconductor, Inc

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