MMPF0100 datasheet(112/136 Pages) FREESCALE

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Analog Integrated Circuit Device Data

112

Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Control Interface I2C Block Description

7.5.6

The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two

pages can be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as

'extended'. On each page, the functional registers are the same, but the extended registers are different. To access registers on

Extended Page 1, one must first write 0x01 to the page register at address 0x7F, and to access registers Extended Page 2, one

must first write 0x02 to the page register at address 0x7F. To access the Functional Page from one of the extended pages, no

write to the page register is necessary.

Registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will have

no effect.

The contents of all registers are given in the tables defined in this chapter; each table is structure as follows:

Name: Name of the bit.

Bit #: The bit location in the register (7-0)

R/W: Read / Write access and control

• R is read-only access

• R/W is read and write access

• RW1C is read and write access with write 1 to clear

Reset: Reset signals are color coded based on the following legend.

Default: The value after reset, as noted in the Default column of the memory map.

• Fixed defaults are explicitly declared as 0 or 1.

• “X” corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if

VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that

may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog

block, for instance the sense bits for the interrupts.

7.5.6.1

Bits reset by SC and VCOREDIG_PORB

Bits reset by PWRON or loaded default or OTP configuration

Bits reset by DIGRESETB

Bits reset by PORB or RESETBMCU

Bits reset by VCOREDIG_PORB

Bits reset by POR or OFFB

Table 135. Functional Page

BITS[7:0]

Add

Name

R/W

Default

DeviceID

8'b0001_0000

–

DEVICE ID [3:0]

SILICONREVID

8'b0001_0000

FULL_LAYER_REV[3:0]

METAL_LAYER_REV[3:0]

FABID

8'b0000_0000

–

FAB[1:0]

FIN[1:0]

INTSTAT0

RW1C 8'b0000_0000

––

THERM130I

THERM125I

THERM120I

THERM110I

LOWVINI

PWRONI

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