STPMC1 datasheet(54/77 Pages) STMICROELECTRONICS

54 / 77 page

Theory of operation

STPMC1

54/77

Doc ID 15728 Rev 6

UXmax = 2

IXmax = 2

There is no differences between status register of x phase in DAx, DRx, DFx, except for first

bit of status register [0]

BIL. This bit indicates no-load condition.

In DAx status register bit

BIL is represents NLC for phase X active energy.

In DRx status register bit

BIL is represents NLC for phase X reactive energy.

In DFx status register bit

BIL is represents NLC for phase X fundamental energy.

In standalone operating mode the 3-ph

BIL signal is available on SCLNLC pin, 3-ph SIGN in

the SYN pin and Tamper flag (is the OR of all tamper conditions - see paragraph

9.10) in

SDATD pin. All the other signals can be read only through SPI interface.

When STPMC1 is used in peripheral mode all these signals can be read through the SPI

interface. See paragraph

9.18 for details on the Status bit location in the STPMC1 data

records.

9.19

Configuration bits map

As indicated in the data records map (see paragraph

9.17), the STPMC1 has 112

configuration bits (CFG data records). Each of them consists of paired elements, one is the

latch (the OTP shadow), and the other is the OTP antifuse element. In this way all the

configuration bits that control the operation of the device can be written in a temporary or

permanent way.

In case of temporary writing the configuration bits values are written in the so-called shadow

registers, which are simple latches that hold the configuration data. The shadow registers

are cleared whenever a reset condition occurs (both POR and remote reset).

In case of permanent writing the configuration bits are stored in the OTP (one time

programmable) cells that keep the information permanently even if the STPMC1 is without

supply, but, once written, they cannot be changed anymore. That's why the CFG are used to

keep critical informations like configuration and calibration values of device. When the

STPMC1 is released all antifuses presents low logic state.

Table 32.

X-phase status bits description

Bit

Name

BIL

No-load Condition not detected

No-load condition detected

BCF

ΣΔ signals alive

One or both

ΣΔ signal stuck

BFR

Frequency of phase voltage is in range

Frequency of line voltage is out of range or voltage

amplitude is below threshold (

LOW = 1)

SIGN

Active energy is negative

Active energy is positive

LIN

Phase 0

≤ u < π

Phase

π ≤ u < 2π

ZRC

After zero crossing

After max value crossing

LOW

Ux > UXmax / 16

Ux < UXmax / 32

NAH

Single Wire Meter mode

IX > IXmax /4096 and BFR==1

Normal operation mode

BFR==0 or IX < IXmax / 8192 and BFR==1

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