STPMC1 datasheet(63/77 Pages) STMICROELECTRONICS

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STPMC1

Theory of operation

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The first read out byte of the data record is the least significant byte (LSB) of the data value

and of course, the fourth byte is the most significant byte (MSB) of the data value. Each byte

can be further divided into a pair of 4-bit nibbles, most and least significant nibble (msn, lsn).

This division makes sense with the MSB of the data value because the msn holds the parity

code.

The sequence of the data record during the reading operation is fixed. However, an

application may apply a precharge command (see mode signal description) prior to the

reading phase. This command increases the group pointer forcing the device to respond

with the next group data records sequence.

The system that reads the data record from the STPMC1 should check the integrity of each

data record, as indicated in paragraph

9.17.8. If the check fails, the reading should be

repeated, but this time only the shifting should be applied; otherwise new data would be

latched into transmission latches, thus losing the previous reading.

Normally, each byte is read out as the most significant bit (msb) first. But this can be

changed by setting the MSBF configuration bit in the STPMC1 CFL data record. If this is

done, each byte is read out as the least significant bit (lsb) first.

9.21.3

Writing procedure

Each writable bit (configuration and mode bits) has its own 7-bit absolute address. For the

configuration bits, the 7-bit address value corresponds to its decimal value, while for the

mode bits the addresses are those indicated in the mode signal paragraph.

In order to change the state of a latch one must send to the STPMC1 a byte of data which is

the normal way to send data via SPI. This byte consists of 1-bit data to be latched (msb),

followed by 7-bit address of destination latch, which makes total 8 bits of command byte, as

summarized in the table below.

Figure 23.

Data records reconstruction

STPMC1 数据表(PDF) 63 Page - STMicroelectronics